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Artigo de periodico
'AL' IND. 2''O' IND. 3' thin film multilayer structure for application in RRAM devices (2018)
Rodrigues, A. N.; Santos, Y. P.; Macedo, M. A.; Rodrigues, Cleber Lima
Source: Solid-State Electronics. Unidade: IF
Subjects: LASER, FÍSICA NUCLEAR, ÍONS
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ABNT
RODRIGUES, A. N. et al. 'AL' IND. 2''O' IND. 3' thin film multilayer structure for application in RRAM devices. Solid-State Electronics, v. no 2018, p. 1-5, 2018Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2018.08.004. Acesso em: 25 abr. 2026.
APA
Rodrigues, A. N., Santos, Y. P., Macedo, M. A., & Rodrigues, C. L. (2018). 'AL' IND. 2''O' IND. 3' thin film multilayer structure for application in RRAM devices. Solid-State Electronics, no 2018, 1-5. doi:10.1016/j.sse.2018.08.004
NLM
Rodrigues AN, Santos YP, Macedo MA, Rodrigues CL. 'AL' IND. 2''O' IND. 3' thin film multilayer structure for application in RRAM devices [Internet]. Solid-State Electronics. 2018 ; no 2018 1-5.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2018.08.004
Vancouver
Rodrigues AN, Santos YP, Macedo MA, Rodrigues CL. 'AL' IND. 2''O' IND. 3' thin film multilayer structure for application in RRAM devices [Internet]. Solid-State Electronics. 2018 ; no 2018 1-5.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2018.08.004
Artigo de periodico
Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs (2015)
Bühler, Rudolf Theoderich; Agopian, Paula Ghedini Der ; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
BÜHLER, Rudolf Theoderich et al. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, v. 103, p. 209-215, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.07.010. Acesso em: 25 abr. 2026.
APA
Bühler, R. T., Agopian, P. G. D., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2015). Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, 103, 209-215. doi:10.1016/j.sse.2014.07.010
NLM
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Vancouver
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Artigo de periodico
Enhanced dynamic threshold voltage UTBB SOI nMOSFETs (2015)
Sasaki, Kátia Regina Akemi; Manini, Matheus Barros; Claeys, Cor ; Simoen, Eddy ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
SASAKI, Kátia Regina Akemi et al. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. Solid-State Electronics, v. 112, p. 19-23, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2015.02.011. Acesso em: 25 abr. 2026.
APA
Sasaki, K. R. A., Manini, M. B., Claeys, C., Simoen, E., & Martino, J. A. (2015). Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. Solid-State Electronics, 112, 19-23. doi:10.1016/j.sse.2015.02.011
NLM
Sasaki KRA, Manini MB, Claeys C, Simoen E, Martino JA. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs [Internet]. Solid-State Electronics. 2015 ; 112 19-23.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2015.02.011
Vancouver
Sasaki KRA, Manini MB, Claeys C, Simoen E, Martino JA. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs [Internet]. Solid-State Electronics. 2015 ; 112 19-23.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2015.02.011
Artigo de periodico
Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism (2015)
Martino, Márcio Dalla Valle; Thean, Aaron; Claeys, Cor ; Neves, Felipe S; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Vandooren, A; Rooyackers, Rita; Simoen, Eddy
Source: Solid-State Electronics. Unidade: EP
Subjects: TRANSISTORES, MICROELETRÔNICA
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ABNT
MARTINO, Márcio Dalla Valle et al. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism. Solid-State Electronics, v. 112, p. 51-55, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2015.02.006. Acesso em: 25 abr. 2026.
APA
Martino, M. D. V., Thean, A., Claeys, C., Neves, F. S., Agopian, P. G. D., Martino, J. A., et al. (2015). Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism. Solid-State Electronics, 112, 51-55. doi:10.1016/j.sse.2015.02.006
NLM
Martino MDV, Thean A, Claeys C, Neves FS, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism [Internet]. Solid-State Electronics. 2015 ; 112 51-55.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2015.02.006
Vancouver
Martino MDV, Thean A, Claeys C, Neves FS, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism [Internet]. Solid-State Electronics. 2015 ; 112 51-55.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2015.02.006
Artigo de periodico
Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics (2014)
Santos, Sara Dereste dos; Martino, João Antonio ; Cretu, B; Strobel, V; Routoure, J.-M; Carin, R; Aoulaiche, Marc; Jurczak, Malgorzata; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Subjects: TEMPERATURA, MICROELETRÔNICA, SILÍCIO
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ABNT
SANTOS, Sara Dereste dos et al. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics. Solid-State Electronics, v. 97, p. 14-22, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.04.034. Acesso em: 25 abr. 2026.
APA
Santos, S. D. dos, Martino, J. A., Cretu, B., Strobel, V., Routoure, J. -M., Carin, R., et al. (2014). Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics. Solid-State Electronics, 97, 14-22. doi:10.1016/j.sse.2014.04.034
NLM
Santos SD dos, Martino JA, Cretu B, Strobel V, Routoure J-M, Carin R, Aoulaiche M, Jurczak M, Claeys C. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics [Internet]. Solid-State Electronics. 2014 ; 97 14-22.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2014.04.034
Vancouver
Santos SD dos, Martino JA, Cretu B, Strobel V, Routoure J-M, Carin R, Aoulaiche M, Jurczak M, Claeys C. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics [Internet]. Solid-State Electronics. 2014 ; 97 14-22.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2014.04.034
Artigo de periodico
Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications (2014)
Sasaki, Karen Lucia Mayumi; Nicoletti, Talitha; Almeida, L M; Santos, Sara Dereste dos; Nissimoff, Albert; Aoulaiche, Marc; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: TRANSISTORES
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ABNT
SASAKI, Karen Lucia Mayumi et al. Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications. Solid-State Electronics, v. 97, p. 30-37, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.04.031. Acesso em: 25 abr. 2026.
APA
Sasaki, K. L. M., Nicoletti, T., Almeida, L. M., Santos, S. D. dos, Nissimoff, A., Aoulaiche, M., & Martino, J. A. (2014). Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications. Solid-State Electronics, 97, 30-37. doi:10.1016/j.sse.2014.04.031
NLM
Sasaki KLM, Nicoletti T, Almeida LM, Santos SD dos, Nissimoff A, Aoulaiche M, Martino JA. Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications [Internet]. Solid-State Electronics. 2014 ;97 30-37.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2014.04.031
Vancouver
Sasaki KLM, Nicoletti T, Almeida LM, Santos SD dos, Nissimoff A, Aoulaiche M, Martino JA. Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications [Internet]. Solid-State Electronics. 2014 ;97 30-37.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2014.04.031
Artigo de periodico
Threshold voltage extraction in Tunnel FETs (2014)
Ortiz-Conde, Adelmo; Martino, João Antonio ; Garcia- Sanchez, Francisco J.; Muci, Juan; Martino, João Antonio ; Agopian, Paula Ghedini Der ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
ORTIZ-CONDE, Adelmo et al. Threshold voltage extraction in Tunnel FETs. Solid-State Electronics, v. 93, p. 49-55, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.12.010. Acesso em: 25 abr. 2026.
APA
Ortiz-Conde, A., Martino, J. A., Garcia- Sanchez, F. J., Muci, J., Martino, J. A., Agopian, P. G. D., & Claeys, C. (2014). Threshold voltage extraction in Tunnel FETs. Solid-State Electronics, 93, 49-55. doi:10.1016/j.sse.2013.12.010
NLM
Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2013.12.010
Vancouver
Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2013.12.010
Artigo de periodico
Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation (2014)
Nicoletti, Talitha; Santos, Sara Dereste dos; Martino, João Antonio ; Aoulaiche, Marc; Veloso, Anabela; Claeys, Cor ; Simoen, Eddy ; Jurczak, Malgorzata
Source: Solid-State Electronics. Unidade: EP
Subjects: TEMPERATURA, MICROELETRÔNICA
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ABNT
NICOLETTI, Talitha et al. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, v. 91, p. 53-58, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.09.012. Acesso em: 25 abr. 2026.
APA
Nicoletti, T., Santos, S. D. dos, Martino, J. A., Aoulaiche, M., Veloso, A., Claeys, C., et al. (2014). Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, 91, 53-58. doi:10.1016/j.sse.2013.09.012
NLM
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Vancouver
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Artigo de periodico
Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates (2013)
Doria, Rodrigo Trevisoli ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor ; Pavanello, Marcelo Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: SILÍCIO
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ABNT
DORIA, Rodrigo Trevisoli et al. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates. Solid-State Electronics, v. 90, p. 121-126, 2013Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.02.042. Acesso em: 25 abr. 2026.
APA
Doria, R. T., Martino, J. A., Simoen, E., Claeys, C., & Pavanello, M. A. (2013). Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates. Solid-State Electronics, 90, 121-126. doi:10.1016/j.sse.2013.02.042
NLM
Doria RT, Martino JA, Simoen E, Claeys C, Pavanello MA. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates [Internet]. Solid-State Electronics. 2013 ; 90 121-126.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2013.02.042
Vancouver
Doria RT, Martino JA, Simoen E, Claeys C, Pavanello MA. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates [Internet]. Solid-State Electronics. 2013 ; 90 121-126.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2013.02.042
Artigo de periodico
Open-circuit voltages: theoretical and experimental optimizations of rear passivated silicon solar cells using Fz and Cz wafers (2010)
Stem, Nair; Ramos, Carlos Alberto Santos; Sánchez, Manuel Cid
Source: Solid-State Electronics. Unidade: EP
Subjects: CIRCUITOS ELÉTRICOS, CÉLULAS SOLARES
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ABNT
STEM, Nair e RAMOS, Carlos Alberto Santos e SÁNCHEZ, Manuel Cid. Open-circuit voltages: theoretical and experimental optimizations of rear passivated silicon solar cells using Fz and Cz wafers. Solid-State Electronics, v. 54, n. 3, p. 221-225, 2010Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2009.09.002. Acesso em: 25 abr. 2026.
APA
Stem, N., Ramos, C. A. S., & Sánchez, M. C. (2010). Open-circuit voltages: theoretical and experimental optimizations of rear passivated silicon solar cells using Fz and Cz wafers. Solid-State Electronics, 54( 3), 221-225. doi:10.1016/j.sse.2009.09.002
NLM
Stem N, Ramos CAS, Sánchez MC. Open-circuit voltages: theoretical and experimental optimizations of rear passivated silicon solar cells using Fz and Cz wafers [Internet]. Solid-State Electronics. 2010 ; 54( 3): 221-225.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2009.09.002
Vancouver
Stem N, Ramos CAS, Sánchez MC. Open-circuit voltages: theoretical and experimental optimizations of rear passivated silicon solar cells using Fz and Cz wafers [Internet]. Solid-State Electronics. 2010 ; 54( 3): 221-225.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2009.09.002
Artigo de periodico
Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs (2010)
Rodrigues, M.; Martino, João Antonio ; Mercha, A.; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Subjects: TRANSISTORES, ELETRODO
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ABNT
RODRIGUES, M. et al. Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs. Solid-State Electronics, v. 54, n. 12, p. 1592-1597, 2010Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2010.07.007. Acesso em: 25 abr. 2026.
APA
Rodrigues, M., Martino, J. A., Mercha, A., Collaert, N., Simoen, E., & Claeys, C. (2010). Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs. Solid-State Electronics, 54( 12), 1592-1597. doi:10.1016/j.sse.2010.07.007
NLM
Rodrigues M, Martino JA, Mercha A, Collaert N, Simoen E, Claeys C. Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs [Internet]. Solid-State Electronics. 2010 ;54( 12): 1592-1597.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2010.07.007
Vancouver
Rodrigues M, Martino JA, Mercha A, Collaert N, Simoen E, Claeys C. Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs [Internet]. Solid-State Electronics. 2010 ;54( 12): 1592-1597.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2010.07.007
Artigo de periodico
SOI technology characterization using SOI-MOS capacitor (2005)
Sonnenberg, Victor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
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ABNT
SONNENBERG, Victor e MARTINO, João Antonio. SOI technology characterization using SOI-MOS capacitor. Solid-State Electronics, 2005Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2004.06.010. Acesso em: 25 abr. 2026.
APA
Sonnenberg, V., & Martino, J. A. (2005). SOI technology characterization using SOI-MOS capacitor. Solid-State Electronics. doi:10.1016/j.sse.2004.06.010
NLM
Sonnenberg V, Martino JA. SOI technology characterization using SOI-MOS capacitor [Internet]. Solid-State Electronics. 2005 ;[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2004.06.010
Vancouver
Sonnenberg V, Martino JA. SOI technology characterization using SOI-MOS capacitor [Internet]. Solid-State Electronics. 2005 ;[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2004.06.010
Artigo de periodico
Physical limitations for homogeneous and highly doped n-type emitter monocrystalline silicon solar cells (2004)
Stem, Nair; Sánchez, Manuel Cid
Source: Solid-State Electronics. Unidade: EP
Subjects: CIRCUITOS ELÉTRICOS, CÉLULAS SOLARES
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ABNT
STEM, Nair e SÁNCHEZ, Manuel Cid. Physical limitations for homogeneous and highly doped n-type emitter monocrystalline silicon solar cells. Solid-State Electronics, v. fe 2004, n. 2, p. 197-205, 2004Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2003.08.005. Acesso em: 25 abr. 2026.
APA
Stem, N., & Sánchez, M. C. (2004). Physical limitations for homogeneous and highly doped n-type emitter monocrystalline silicon solar cells. Solid-State Electronics, fe 2004( 2), 197-205. doi:10.1016/j.sse.2003.08.005
NLM
Stem N, Sánchez MC. Physical limitations for homogeneous and highly doped n-type emitter monocrystalline silicon solar cells [Internet]. Solid-State Electronics. 2004 ; fe 2004( 2): 197-205.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2003.08.005
Vancouver
Stem N, Sánchez MC. Physical limitations for homogeneous and highly doped n-type emitter monocrystalline silicon solar cells [Internet]. Solid-State Electronics. 2004 ; fe 2004( 2): 197-205.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/j.sse.2003.08.005
Artigo de periodico
Analog circuit design using graded-channel silicon-on-insulator nMOSFETs (2002)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS ANALÓGICOS
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ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, v. 46, n. 8, p. 1215-1225, 2002Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(02)00020-5. Acesso em: 25 abr. 2026.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2002). Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, 46( 8), 1215-1225. doi:10.1016/s0038-1101(02)00020-5
NLM
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5
Vancouver
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5
Artigo de periodico
Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices (2002)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: FILMES FINOS
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ABNT
NICOLETT, Aparecido Sirley et al. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices. Solid-State Electronics, n. 9, p. 1381-1387, 2002Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(02)00067-9. Acesso em: 25 abr. 2026.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2002). Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices. Solid-State Electronics, ( 9), 1381-1387. doi:10.1016/s0038-1101(02)00067-9
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices [Internet]. Solid-State Electronics. 2002 ;( 9): 1381-1387.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(02)00067-9
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices [Internet]. Solid-State Electronics. 2002 ;( 9): 1381-1387.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(02)00067-9
Artigo de periodico
Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures (2001)
Bellodi, Marcello; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
BELLODI, Marcello e MARTINO, João Antonio. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, v. 45, n. 5, p. 683-688, 2001Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(01)00099-5. Acesso em: 25 abr. 2026.
APA
Bellodi, M., & Martino, J. A. (2001). Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, 45( 5), 683-688. doi:10.1016/s0038-1101(01)00099-5
NLM
Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5
Vancouver
Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5
Artigo de periodico
A poly(acetoxy-`rô´-phenylene vinylene) based diode with a soft breakdown behaviour (2000)
Lima, J. R. de; Péres, Laura Oliveira; Garcia, Jarem Raul; Gruber, Jonas ; Hümmelgen, Ivo Alexandre
Source: Solid-State Electronics. Unidade: IQ
Assunto: QUÍMICA ORGÂNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
LIMA, J. R. de et al. A poly(acetoxy-`rô´-phenylene vinylene) based diode with a soft breakdown behaviour. Solid-State Electronics, v. 44, n. 3, p. 565-569, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00290-7. Acesso em: 25 abr. 2026.
APA
Lima, J. R. de, Péres, L. O., Garcia, J. R., Gruber, J., & Hümmelgen, I. A. (2000). A poly(acetoxy-`rô´-phenylene vinylene) based diode with a soft breakdown behaviour. Solid-State Electronics, 44( 3), 565-569. doi:10.1016/s0038-1101(99)00290-7
NLM
Lima JR de, Péres LO, Garcia JR, Gruber J, Hümmelgen IA. A poly(acetoxy-`rô´-phenylene vinylene) based diode with a soft breakdown behaviour [Internet]. Solid-State Electronics. 2000 ; 44( 3): 565-569.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(99)00290-7
Vancouver
Lima JR de, Péres LO, Garcia JR, Gruber J, Hümmelgen IA. A poly(acetoxy-`rô´-phenylene vinylene) based diode with a soft breakdown behaviour [Internet]. Solid-State Electronics. 2000 ; 44( 3): 565-569.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(99)00290-7
Artigo de periodico
Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, v. No 2000, n. 11, p. 1961-1969, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00166-0. Acesso em: 25 abr. 2026.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, No 2000( 11), 1961-1969. doi:10.1016/s0038-1101(00)00166-0
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Artigo de periodico
Analog performance and application of graded-channel fully depleted SOI MOSFETs (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, v. 44, n. 7, p. 1219-1222, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00034-4. Acesso em: 25 abr. 2026.
APA
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, 44( 7), 1219-1222. doi:10.1016/s0038-1101(00)00034-4
NLM
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Vancouver
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Artigo de periodico
Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, v. 44, n. 6, p. 917-922, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00032-0. Acesso em: 25 abr. 2026.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44( 6), 917-922. doi:10.1016/s0038-1101(00)00032-0
NLM
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0
Vancouver
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2026 abr. 25 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0

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