Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates (2013)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- DOI: 10.1016/j.sse.2013.02.042
- Assunto: SILÍCIO
- Language: Inglês
- Source:
- Título: Solid-State Electronics
- Volume/Número/Paginação/Ano: v. 90, p. 121-126, Dec 2013
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
DORIA, Rodrigo Trevisoli et al. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates. Solid-State Electronics, v. 90, p. 121-126, 2013Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.02.042. Acesso em: 20 jan. 2026. -
APA
Doria, R. T., Martino, J. A., Simoen, E., Claeys, C., & Pavanello, M. A. (2013). Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates. Solid-State Electronics, 90, 121-126. doi:10.1016/j.sse.2013.02.042 -
NLM
Doria RT, Martino JA, Simoen E, Claeys C, Pavanello MA. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates [Internet]. Solid-State Electronics. 2013 ; 90 121-126.[citado 2026 jan. 20 ] Available from: https://doi.org/10.1016/j.sse.2013.02.042 -
Vancouver
Doria RT, Martino JA, Simoen E, Claeys C, Pavanello MA. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates [Internet]. Solid-State Electronics. 2013 ; 90 121-126.[citado 2026 jan. 20 ] Available from: https://doi.org/10.1016/j.sse.2013.02.042 - A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs
- Sidewall angle influence on the finFET analog parameters
- Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures
- Low temperature operation of undoped body triple-gate finFETs from an analog perspective
- Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs
Informações sobre o DOI: 10.1016/j.sse.2013.02.042 (Fonte: oaDOI API)
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