Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments (2005)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2005
- Source:
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
PAVANELLO, Marcelo Antonio et al. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 20 jan. 2026. -
APA
Pavanello, M. A., Cerdeira, A., Martino, J. A., Alemán, M. A., & Flandre, D. (2005). Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2026 jan. 20 ] -
Vancouver
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2026 jan. 20 ] - A simple analytical model of graded-channel SOI nMOSFET transconductance
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs
- Sidewall angle influence on the finFET analog parameters
- Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures
- Low temperature operation of undoped body triple-gate finFETs from an analog perspective
- Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs
- Behavior of graded-channel fully depleted SOI NMOSFET at high temperatures
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