Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments (2005)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2005
- Source:
- Título do periódico: Microelectronics Technology and Devices SBMICRO 2005
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
PAVANELLO, Marcelo Antonio et al. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 23 abr. 2024. -
APA
Pavanello, M. A., Cerdeira, A., Martino, J. A., Alemán, M. A., & Flandre, D. (2005). Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 abr. 23 ] -
Vancouver
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 abr. 23 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Analysis of deep submicrometer bulk and fully depleted soi nmosfet analog operation at cryogenic temperatures
- Physical characterization and reliability aspects of MuGFETs
- A study on the self-heating effect in deep-submicrometer partially depleted SOI MOSFETs at low temperatures
- Halo effect on 0.13 'mu'm floating-body partially depleted SOI n-Mosfets in low temperature operation
- Analog circuit design using graded-channel silicon-on-insulator nMOSFETs
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