Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature (2016)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- DOI: 10.1088/0268-1242/31/11/114005
- Subjects: SILÍCIO; SEMICONDUTORES
- Language: Inglês
- Source:
- Título: Semiconductor Science and Technology
- Volume/Número/Paginação/Ano: v. 31, n. 11, p. 114005, 2016
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
PAVANELLO, Marcelo Antonio et al. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature. Semiconductor Science and Technology, v. 31, n. 11, p. 114005, 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/11/114005. Acesso em: 23 jan. 2026. -
APA
Pavanello, M. A., Souza, M. de, Ribeiro, T. A., Martino, J. A., & Flandre, D. (2016). Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature. Semiconductor Science and Technology, 31( 11), 114005. doi:10.1088/0268-1242/31/11/114005 -
NLM
Pavanello MA, Souza M de, Ribeiro TA, Martino JA, Flandre D. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114005.[citado 2026 jan. 23 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114005 -
Vancouver
Pavanello MA, Souza M de, Ribeiro TA, Martino JA, Flandre D. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114005.[citado 2026 jan. 23 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114005 - Analog performance of graded-channel SOI NMOSFETS at low temperatures
- A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Behavior of graded-channel fully depleted SOI NMOSFET at high temperatures
- Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs
- Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs
- Sidewall angle influence on the finFET analog parameters
Informações sobre o DOI: 10.1088/0268-1242/31/11/114005 (Fonte: oaDOI API)
How to cite
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
