Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs (2003)
- Authors:
- USP affiliated authors: MARTINO, JOAO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher: IEEE Computer Society
- Publisher place: Piscataway
- Date published: 2003
- Source:
- Título: SBCCI 03 : proceedings
- Conference titles: Symposium on Integrated Circuits and Systems Design
-
ABNT
GIMENEZ, Salvador Pinillos et al. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs. 2003, Anais.. Piscataway: IEEE Computer Society, 2003. . Acesso em: 05 jan. 2026. -
APA
Gimenez, S. P., Pavanello, M. A., Martino, J. A., Adriaensen, S., & Flandre, D. (2003). Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs. In SBCCI 03 : proceedings. Piscataway: IEEE Computer Society. -
NLM
Gimenez SP, Pavanello MA, Martino JA, Adriaensen S, Flandre D. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs. SBCCI 03 : proceedings. 2003 ;[citado 2026 jan. 05 ] -
Vancouver
Gimenez SP, Pavanello MA, Martino JA, Adriaensen S, Flandre D. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs. SBCCI 03 : proceedings. 2003 ;[citado 2026 jan. 05 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
- Low temperature operation of graded-channel SOI nMOSFETs for analog applications
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