Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation (2004)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Source:
- Título: Proceedings
- Conference titles: European Workshop on Low Temperature Electronics
-
ABNT
PAVANELLO, Marcelo Antonio et al. Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation. 2004, Anais.. Noordwijk: Escola Politécnica, Universidade de São Paulo, 2004. . Acesso em: 05 jan. 2026. -
APA
Pavanello, M. A., Martino, J. A., Simoen, E., & Claeys, C. (2004). Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation. In Proceedings. Noordwijk: Escola Politécnica, Universidade de São Paulo. -
NLM
Pavanello MA, Martino JA, Simoen E, Claeys C. Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation. Proceedings. 2004 ;[citado 2026 jan. 05 ] -
Vancouver
Pavanello MA, Martino JA, Simoen E, Claeys C. Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation. Proceedings. 2004 ;[citado 2026 jan. 05 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
- Low temperature operation of graded-channel SOI nMOSFETs for analog applications
How to cite
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
