Operation of double gate graded-channel transistors at low temperatures (2003)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2003
- Source:
- Título: Proceedings
- Conference titles: International Symposium on Low Temperature Electronics
-
ABNT
PAVANELLO, Marcelo Antonio et al. Operation of double gate graded-channel transistors at low temperatures. 2003, Anais.. Pennington: The Electrochemical Society, 2003. . Acesso em: 11 fev. 2026. -
APA
Pavanello, M. A., Martino, J. A., Chung, T. M., Kranti, A., Raskin, J. -P., & Flandre, D. (2003). Operation of double gate graded-channel transistors at low temperatures. In Proceedings. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Martino JA, Chung TM, Kranti A, Raskin J-P, Flandre D. Operation of double gate graded-channel transistors at low temperatures. Proceedings. 2003 ;[citado 2026 fev. 11 ] -
Vancouver
Pavanello MA, Martino JA, Chung TM, Kranti A, Raskin J-P, Flandre D. Operation of double gate graded-channel transistors at low temperatures. Proceedings. 2003 ;[citado 2026 fev. 11 ] - Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
- Analysis on GC SOI MOSFET analog parameters at high temperatures
- Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Behavior of graded-channel fully depleted SOI NMOSFET at high temperatures
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