Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics (2014)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- DOI: 10.1016/j.sse.2014.04.034
- Subjects: TEMPERATURA; MICROELETRÔNICA; SILÍCIO
- Language: Inglês
- Source:
- Título: Solid-State Electronics
- Volume/Número/Paginação/Ano: v. 97, p. 14-22, July 2014
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
SANTOS, Sara Dereste dos et al. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics. Solid-State Electronics, v. 97, p. 14-22, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.04.034. Acesso em: 20 jan. 2026. -
APA
Santos, S. D. dos, Martino, J. A., Cretu, B., Strobel, V., Routoure, J. -M., Carin, R., et al. (2014). Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics. Solid-State Electronics, 97, 14-22. doi:10.1016/j.sse.2014.04.034 -
NLM
Santos SD dos, Martino JA, Cretu B, Strobel V, Routoure J-M, Carin R, Aoulaiche M, Jurczak M, Claeys C. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics [Internet]. Solid-State Electronics. 2014 ; 97 14-22.[citado 2026 jan. 20 ] Available from: https://doi.org/10.1016/j.sse.2014.04.034 -
Vancouver
Santos SD dos, Martino JA, Cretu B, Strobel V, Routoure J-M, Carin R, Aoulaiche M, Jurczak M, Claeys C. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics [Internet]. Solid-State Electronics. 2014 ; 97 14-22.[citado 2026 jan. 20 ] Available from: https://doi.org/10.1016/j.sse.2014.04.034 - Analog performance and application of graded-channel fully depleted SOI MOSFETs
- Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects
- Projeto de processos de fabricação avançados aplicáveis nas tecnologias CMOS micrométricas
- Simple method to determine the poly gate doping concentration based on poly depletion effect
- A new technique to extract the oxide charge density at front and back interfaces of SOI nMOSFETs devices
- Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET
- A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region
- A simple method to model nonrectangular-gate layout in SOI MOSFETs
- New leakage drain current model for high temperature soi mesfet
- Influence of the substrate potential drop on fully depleted soi mesfet threshold voltage at 77k
Informações sobre o DOI: 10.1016/j.sse.2014.04.034 (Fonte: oaDOI API)
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