Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k (1995)
- Authors:
- Autor USP: MARTINO, JOAO ANTONIO - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher: Instituto de Informatica da Ufrgs
- Publisher place: Porto Alegre
- Date published: 1995
- Source:
- Título: Proceedings
- Conference titles: Congress of the Brazilian Microelectronics Society
-
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k. 1995, Anais.. Porto Alegre: Instituto de Informatica da Ufrgs, 1995. . Acesso em: 06 fev. 2026. -
APA
Pavanello, M. A., & Martino, J. A. (1995). Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k. In Proceedings. Porto Alegre: Instituto de Informatica da Ufrgs. -
NLM
Pavanello MA, Martino JA. Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k. Proceedings. 1995 ;[citado 2026 fev. 06 ] -
Vancouver
Pavanello MA, Martino JA. Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k. Proceedings. 1995 ;[citado 2026 fev. 06 ] - Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance
- Caracterização elétrica de dispositivos SOI MOS em baixa temperatura
- Metodo simples para a obtencao da densidade de armadilhas na primeira e segunda interface em soi-mosfet
- Combined l and series resistance extraction of ldd mosfets
- Influencia da temperatura em transistores soi (silicon on insulator) mosfets
- The impact of gate length scaling on UTBOX FDSOI devices: the digital/analog performance of extension-less structures
- Simple method for the determination of the interface trap density at 77k in fully depleted acumulation mode soi mosfets
- Transistor soi-nmosfet nao auto-alinhado
- Impact of selective epitaxial growth and uniaxial/biaxial strain on DIBL effect using triple gate FinFETs
- Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics
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