Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs (2000)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- DOI: 10.1016/s0038-1101(00)00166-0
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher place: Kidlington
- Date published: 2000
- Source:
- Título: Solid-State Electronics
- ISSN: 0038-1101
- Volume/Número/Paginação/Ano: v. 44, n. 11, p. 1961-1969, Nov. 2000
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
NICOLETT, Aparecido Sirley et al. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, v. No 2000, n. 11, p. 1961-1969, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00166-0. Acesso em: 23 jan. 2026. -
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, No 2000( 11), 1961-1969. doi:10.1016/s0038-1101(00)00166-0 -
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2026 jan. 23 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0 -
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2026 jan. 23 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0 - Analog circuit design using graded-channel SOI NMOSFETs
- Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures
- Extraction of the interface and oxide charge density in silicon-on-insulator MOSFETs
- Projeto de um processo CMOS com cavidade dupla e dimensões de porta de 2 um
- Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
- Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation
- Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results
- Estudo comparativo de estruturas de fonte e dreno de transistores mos submicrometricos
- Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices
- Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs
Informações sobre o DOI: 10.1016/s0038-1101(00)00166-0 (Fonte: oaDOI API)
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