Analog circuit design using graded-channel silicon-on-insulator nMOSFETs (2002)
- Authors:
- USP affiliated authors: MARTINO, JOAO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- DOI: 10.1016/s0038-1101(02)00020-5
- Assunto: CIRCUITOS ANALÓGICOS
- Language: Inglês
- Imprenta:
- Source:
- Título: Solid-State Electronics
- ISSN: 0038-1101
- Volume/Número/Paginação/Ano: v. 46, n. 8, p. 1215-1225, August 2002
- Status:
- Nenhuma versão em acesso aberto identificada
-
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, v. 46, n. 8, p. 1215-1225, 2002Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(02)00020-5. Acesso em: 24 mar. 2026. -
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2002). Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, 46( 8), 1215-1225. doi:10.1016/s0038-1101(02)00020-5 -
NLM
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2026 mar. 24 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5 -
Vancouver
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2026 mar. 24 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5 - Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
- Analysis on GC SOI MOSFET analog parameters at high temperatures
- Operation of double gate graded-channel transistors at low temperatures
- Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
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