Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects (2000)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- DOI: 10.1016/s0038-1101(00)00032-0
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher place: Kidlington
- Date published: 2000
- Source:
- Título: Solid-State Electronics
- ISSN: 0038-1101
- Volume/Número/Paginação/Ano: v. 44, n. 6, p. 917-922, June 2000
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, v. 44, n. 6, p. 917-922, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00032-0. Acesso em: 20 jan. 2026. -
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44( 6), 917-922. doi:10.1016/s0038-1101(00)00032-0 -
NLM
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2026 jan. 20 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0 -
Vancouver
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2026 jan. 20 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0 - Analog performance and application of graded-channel fully depleted SOI MOSFETs
- Projeto de processos de fabricação avançados aplicáveis nas tecnologias CMOS micrométricas
- Simple method to determine the poly gate doping concentration based on poly depletion effect
- A new technique to extract the oxide charge density at front and back interfaces of SOI nMOSFETs devices
- Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET
- A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region
- A simple method to model nonrectangular-gate layout in SOI MOSFETs
- New leakage drain current model for high temperature soi mesfet
- Influence of the substrate potential drop on fully depleted soi mesfet threshold voltage at 77k
- A simple model for a new SOI MOSFET with asymmetric trapezoidal gate
Informações sobre o DOI: 10.1016/s0038-1101(00)00032-0 (Fonte: oaDOI API)
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