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Trabalho de evento
Low-cost ultraviolet radiation sensor using epoxy-resin optical filters over MOS photodiodes (2023)
Santos, Fernando L Nogueira; Santos Filho, Sebastião Gomes dos ; Martino, João Antonio
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices. Unidade: EP
Subjects: SENSOR, RADIAÇÃO ULTRAVIOLETA
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SANTOS, Fernando L Nogueira e SANTOS FILHO, Sebastião Gomes dos e MARTINO, João Antonio. Low-cost ultraviolet radiation sensor using epoxy-resin optical filters over MOS photodiodes. 2023, Anais.. [Piscataway]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302558. Acesso em: 06 jul. 2024.
APA
Santos, F. L. N., Santos Filho, S. G. dos, & Martino, J. A. (2023). Low-cost ultraviolet radiation sensor using epoxy-resin optical filters over MOS photodiodes. In SBMicro. [Piscataway]: IEEE. doi:10.1109/SBMicro60499.2023.10302558
NLM
Santos FLN, Santos Filho SG dos, Martino JA. Low-cost ultraviolet radiation sensor using epoxy-resin optical filters over MOS photodiodes [Internet]. SBMicro. 2023 ;[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302558
Vancouver
Santos FLN, Santos Filho SG dos, Martino JA. Low-cost ultraviolet radiation sensor using epoxy-resin optical filters over MOS photodiodes [Internet]. SBMicro. 2023 ;[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302558
Artigo de periodico
Back gate bias influence on BESOI ISFET sensitivity (2023)
Duarte, Pedro Henrique; Rangel, Ricardo Cardoso; Ramos, Daniel Augusto; Yojo, Leonardo Shimizu; Sasaki, Kátia Regina Akemi ; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: ECS Transactions. Unidade: EP
Subjects: ELETRODO, REFRATÁRIOS, METALOGRAFIA
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DUARTE, Pedro Henrique et al. Back gate bias influence on BESOI ISFET sensitivity. ECS Transactions, v. 111, n. 1, p. 279-284, 2023Tradução . . Disponível em: https://doi.org/10.1149/11101.0279ecst. Acesso em: 06 jul. 2024.
APA
Duarte, P. H., Rangel, R. C., Ramos, D. A., Yojo, L. S., Sasaki, K. R. A., Agopian, P. G. D., & Martino, J. A. (2023). Back gate bias influence on BESOI ISFET sensitivity. ECS Transactions, 111( 1), 279-284. doi:10.1149/11101.0279ecst
NLM
Duarte PH, Rangel RC, Ramos DA, Yojo LS, Sasaki KRA, Agopian PGD, Martino JA. Back gate bias influence on BESOI ISFET sensitivity [Internet]. ECS Transactions. 2023 ; 111( 1): 279-284.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1149/11101.0279ecst
Vancouver
Duarte PH, Rangel RC, Ramos DA, Yojo LS, Sasaki KRA, Agopian PGD, Martino JA. Back gate bias influence on BESOI ISFET sensitivity [Internet]. ECS Transactions. 2023 ; 111( 1): 279-284.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1149/11101.0279ecst
Trabalho de evento
Temperature influence on operational transconductance amplifier designed with triple gate TFET (2022)
Camargo, Raphael Gil; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: SBMICRO. Conference titles: Symposium on Microelectronics Technology. Unidade: EP
Subjects: ANÁLISE TÉRMICA, AMPLIFICADORES
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CAMARGO, Raphael Gil e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Temperature influence on operational transconductance amplifier designed with triple gate TFET. 2022, Anais.. Piscataway: IEEE, 2022. Disponível em: https://doi.org/10.1109/SBMICRO55822.2022.9880962. Acesso em: 06 jul. 2024.
APA
Camargo, R. G., Martino, J. A., & Agopian, P. G. D. (2022). Temperature influence on operational transconductance amplifier designed with triple gate TFET. In SBMICRO. Piscataway: IEEE. doi:10.1109/SBMICRO55822.2022.9880962
NLM
Camargo RG, Martino JA, Agopian PGD. Temperature influence on operational transconductance amplifier designed with triple gate TFET [Internet]. SBMICRO. 2022 ;[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9880962
Vancouver
Camargo RG, Martino JA, Agopian PGD. Temperature influence on operational transconductance amplifier designed with triple gate TFET [Internet]. SBMICRO. 2022 ;[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9880962
Trabalho de evento
Nanowire TFET with different source compositions applied to low-dropout voltage regulator (2022)
Toledo, Rodrigo do Nascimento; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: SBMICRO. Conference titles: Symposium on Microelectronics Technology. Unidade: EP
Subjects: TRANSISTORES, NANOELETRÔNICA, CIRCUITOS ANALÓGICOS
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TOLEDO, Rodrigo do Nascimento e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Nanowire TFET with different source compositions applied to low-dropout voltage regulator. 2022, Anais.. Piscataway: IEEE, 2022. p. 1-4. Disponível em: https://www.doi.org/10.1109/SBMICRO55822.2022.9881035. Acesso em: 06 jul. 2024.
APA
Toledo, R. do N., Martino, J. A., & Agopian, P. G. D. (2022). Nanowire TFET with different source compositions applied to low-dropout voltage regulator. In SBMICRO (p. 1-4). Piscataway: IEEE. doi:10.1109/SBMICRO55822.2022.9881035
NLM
Toledo R do N, Martino JA, Agopian PGD. Nanowire TFET with different source compositions applied to low-dropout voltage regulator [Internet]. SBMICRO. 2022 ; 1-4.[citado 2024 jul. 06 ] Available from: https://www.doi.org/10.1109/SBMICRO55822.2022.9881035
Vancouver
Toledo R do N, Martino JA, Agopian PGD. Nanowire TFET with different source compositions applied to low-dropout voltage regulator [Internet]. SBMICRO. 2022 ; 1-4.[citado 2024 jul. 06 ] Available from: https://www.doi.org/10.1109/SBMICRO55822.2022.9881035
Trabalho de evento
Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's (2022)
Ribeiro, Arllen D.R.; Araújo, Gustavo Vinicius de; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: SBMICRO. Conference titles: Symposium on Microelectronics Technology. Unidade: EP
Subjects: MICROELETRÔNICA, SILÍCIO, INOVAÇÕES TECNOLÓGICAS
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RIBEIRO, Arllen D.R. et al. Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's. 2022, Anais.. Piscataway: IEEE, 2022. Disponível em: https://doi.org/10.1109/SBMICRO55822.2022.9881005. Acesso em: 06 jul. 2024.
APA
Ribeiro, A. D. R., Araújo, G. V. de, Martino, J. A., & Agopian, P. G. D. (2022). Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's. In SBMICRO. Piscataway: IEEE. doi:10.1109/SBMICRO55822.2022.9881005
NLM
Ribeiro ADR, Araújo GV de, Martino JA, Agopian PGD. Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's [Internet]. SBMICRO. 2022 ;[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9881005
Vancouver
Ribeiro ADR, Araújo GV de, Martino JA, Agopian PGD. Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's [Internet]. SBMICRO. 2022 ;[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9881005
Trabalho de evento
Experimental behavior of line-TFET applied to low-dropout voltage regulator (2022)
Silva, Wenita de Lima; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: SBMICRO: proceedings. Conference titles: Symposium on Microelectronics Technology. Unidade: EP
Subjects: SEMICONDUTORES, ESTABILIDADE, CIRCUITOS ANALÓGICOS
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SILVA, Wenita de Lima e AGOPIAN, Paula Ghedini Der e MARTINO, João Antonio. Experimental behavior of line-TFET applied to low-dropout voltage regulator. 2022, Anais.. [s.L.]: IEEE, 2022. Disponível em: https://doi.org/10.1109/SBMICRO55822.2022.9881041. Acesso em: 06 jul. 2024.
APA
Silva, W. de L., Agopian, P. G. D., & Martino, J. A. (2022). Experimental behavior of line-TFET applied to low-dropout voltage regulator. In SBMICRO: proceedings. [s.L.]: IEEE. doi:10.1109/SBMICRO55822.2022.9881041
NLM
Silva W de L, Agopian PGD, Martino JA. Experimental behavior of line-TFET applied to low-dropout voltage regulator [Internet]. SBMICRO: proceedings. 2022 ;[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9881041
Vancouver
Silva W de L, Agopian PGD, Martino JA. Experimental behavior of line-TFET applied to low-dropout voltage regulator [Internet]. SBMICRO: proceedings. 2022 ;[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9881041
Trabalho de evento
Monte Carlo analysis of a fractional-order MOS capacitor using fractal tree implementation (2022)
Fernandes, Lucas Almir dos Santos; Alayo Chávez, Marco Isaías ; Martino, João Antonio
Source: SBMICRO. Conference titles: Symposium on Microelectronics Technology. Unidade: EP
Subjects: FRACTAIS, MÉTODO DE MONTE CARLO, SIMULAÇÃO
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FERNANDES, Lucas Almir dos Santos e ALAYO CHÁVEZ, Marco Isaías e MARTINO, João Antonio. Monte Carlo analysis of a fractional-order MOS capacitor using fractal tree implementation. 2022, Anais.. Piscataway: IEEE, 2022. p. 1-4. Disponível em: https://www.doi.org/10.1109/SBMICRO55822.2022.9881030. Acesso em: 06 jul. 2024.
APA
Fernandes, L. A. dos S., Alayo Chávez, M. I., & Martino, J. A. (2022). Monte Carlo analysis of a fractional-order MOS capacitor using fractal tree implementation. In SBMICRO (p. 1-4). Piscataway: IEEE. doi:10.1109/SBMICRO55822.2022.9881030
NLM
Fernandes LA dos S, Alayo Chávez MI, Martino JA. Monte Carlo analysis of a fractional-order MOS capacitor using fractal tree implementation [Internet]. SBMICRO. 2022 ; 1-4.[citado 2024 jul. 06 ] Available from: https://www.doi.org/10.1109/SBMICRO55822.2022.9881030
Vancouver
Fernandes LA dos S, Alayo Chávez MI, Martino JA. Monte Carlo analysis of a fractional-order MOS capacitor using fractal tree implementation [Internet]. SBMICRO. 2022 ; 1-4.[citado 2024 jul. 06 ] Available from: https://www.doi.org/10.1109/SBMICRO55822.2022.9881030
Trabalho de evento
Experimental analysis of MISHEMT multiple conductions from 200K to 450K (2022)
Perina, Welder Fernandes; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: SBMICRO. Conference titles: Symposium on Microelectronics Technology. Unidade: EP
Subjects: TRANSISTORES, TEMPERATURA
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PERINA, Welder Fernandes e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Experimental analysis of MISHEMT multiple conductions from 200K to 450K. 2022, Anais.. Piscataway: IEEE, 2022. p. 1-4. Disponível em: https://www.doi.org/10.1109/SBMICRO55822.2022.9881049. Acesso em: 06 jul. 2024.
APA
Perina, W. F., Martino, J. A., & Agopian, P. G. D. (2022). Experimental analysis of MISHEMT multiple conductions from 200K to 450K. In SBMICRO (p. 1-4). Piscataway: IEEE. doi:10.1109/SBMICRO55822.2022.9881049
NLM
Perina WF, Martino JA, Agopian PGD. Experimental analysis of MISHEMT multiple conductions from 200K to 450K [Internet]. SBMICRO. 2022 ; 1-4.[citado 2024 jul. 06 ] Available from: https://www.doi.org/10.1109/SBMICRO55822.2022.9881049
Vancouver
Perina WF, Martino JA, Agopian PGD. Experimental analysis of MISHEMT multiple conductions from 200K to 450K [Internet]. SBMICRO. 2022 ; 1-4.[citado 2024 jul. 06 ] Available from: https://www.doi.org/10.1109/SBMICRO55822.2022.9881049
Artigo de periodico
Performance of differential pair circuits designed with line tunnel FET devices at different temperatures (2018)
Martino, Márcio Dalla Valle; Claeys, Cor ; Agopian, Paula Ghedini Der ; Rooyackers, Rita; Simoen, Eddy ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Assunto: SEMICONDUTORES
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MARTINO, Márcio Dalla Valle et al. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, v. 33, n. 7, p. 075012, 2018Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/aac4fd. Acesso em: 06 jul. 2024.
APA
Martino, M. D. V., Claeys, C., Agopian, P. G. D., Rooyackers, R., Simoen, E., & Martino, J. A. (2018). Performance of differential pair circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, 33( 7), 075012. doi:10.1088/1361-6641/aac4fd
NLM
Martino MDV, Claeys C, Agopian PGD, Rooyackers R, Simoen E, Martino JA. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2018 ; 33( 7): 075012.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/1361-6641/aac4fd
Vancouver
Martino MDV, Claeys C, Agopian PGD, Rooyackers R, Simoen E, Martino JA. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2018 ; 33( 7): 075012.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/1361-6641/aac4fd
Artigo de periodico
Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K (2018)
Caparroz, Luís Felipe Vicentis; Agopian, Paula Ghedini Der ; Claeys, Cor ; Simoen, Eddy ; Bordallo, Caio Cesar Mendes ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidades: EP, EACH
Subjects: TEMPERATURA, SEMICONDUTORES
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CAPARROZ, Luís Felipe Vicentis et al. Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K. Semiconductor Science and Technology, v. 33, n. 6, p. 065003, 2018Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/aabab3. Acesso em: 06 jul. 2024.
APA
Caparroz, L. F. V., Agopian, P. G. D., Claeys, C., Simoen, E., Bordallo, C. C. M., & Martino, J. A. (2018). Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K. Semiconductor Science and Technology, 33( 6), 065003. doi:10.1088/1361-6641/aabab3
NLM
Caparroz LFV, Agopian PGD, Claeys C, Simoen E, Bordallo CCM, Martino JA. Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K [Internet]. Semiconductor Science and Technology. 2018 ; 33( 6): 065003.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/1361-6641/aabab3
Vancouver
Caparroz LFV, Agopian PGD, Claeys C, Simoen E, Bordallo CCM, Martino JA. Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K [Internet]. Semiconductor Science and Technology. 2018 ; 33( 6): 065003.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/1361-6641/aabab3
Artigo de periodico
The impact of the temperature on In0.53Ga0.47As nTFETs (2018)
Bordallo, Caio Cesar Mendes ; Mocuta, Dan; Collaert, Nadine ; Alian, A; Simoen, Eddy ; Claeys, Cor ; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Rooyackers, Rita; Mols, Yannick; Van Dooren, A; Verhulst, Anne S; Lin, D
Source: Composants nanoélectroniques. Unidade: EP
Assunto: SEMICONDUTORES
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BORDALLO, Caio Cesar Mendes et al. The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques, v. 18, n. 1, 2018Tradução . . Disponível em: https://doi.org/10.21494/iste.op.2018.0224. Acesso em: 06 jul. 2024.
APA
Bordallo, C. C. M., Mocuta, D., Collaert, N., Alian, A., Simoen, E., Claeys, C., et al. (2018). The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques, 18( 1). doi:10.21494/iste.op.2018.0224
NLM
Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):[citado 2024 jul. 06 ] Available from: https://doi.org/10.21494/iste.op.2018.0224
Vancouver
Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):[citado 2024 jul. 06 ] Available from: https://doi.org/10.21494/iste.op.2018.0224
Artigo de periodico
Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies (2017)
Itocazu, Vitor Tatsuo ; Sonnenberg, Victor ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: SEMICONDUTORES
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ITOCAZU, Vitor Tatsuo et al. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems, v. 12, n. 2, p. 82-88, 2017Tradução . . Disponível em: https://doi.org/10.29292/jics.v12i2.455. Acesso em: 06 jul. 2024.
APA
Itocazu, V. T., Sonnenberg, V., Martino, J. A., Simoen, E., & Claeys, C. (2017). Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems, 12( 2), 82-88. doi:10.29292/jics.v12i2.455
NLM
Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies [Internet]. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.[citado 2024 jul. 06 ] Available from: https://doi.org/10.29292/jics.v12i2.455
Vancouver
Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies [Internet]. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.[citado 2024 jul. 06 ] Available from: https://doi.org/10.29292/jics.v12i2.455
Artigo de periodico
Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures (2017)
Martino, Márcio Dalla Valle; Claeys, Cor ; Rooyackers, Rita; Simoen, Eddy ; Agopian, Paula Ghedini Der ; Vandooren, A; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
MARTINO, Márcio Dalla Valle et al. Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, v. 32, n. 5, p. 055015, 2017Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/aa6764. Acesso em: 06 jul. 2024.
APA
Martino, M. D. V., Claeys, C., Rooyackers, R., Simoen, E., Agopian, P. G. D., Vandooren, A., & Martino, J. A. (2017). Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, 32( 5), 055015. doi:10.1088/1361-6641/aa6764
NLM
Martino MDV, Claeys C, Rooyackers R, Simoen E, Agopian PGD, Vandooren A, Martino JA. Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2017 ; 32( 5): 055015.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/1361-6641/aa6764
Vancouver
Martino MDV, Claeys C, Rooyackers R, Simoen E, Agopian PGD, Vandooren A, Martino JA. Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2017 ; 32( 5): 055015.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/1361-6641/aa6764
Artigo de periodico
The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs (2017)
Bordallo, Caio Cesar Mendes ; Collaert, Nadine ; Claeys, Cor ; Simoen, Eddy ; Vandooren, A; Rooyackers, Rita; Mols, Yannick; Alian, A; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: IEEE Transactions on Electron Devices. Unidade: EP
Subjects: MICROELETRÔNICA, SEMICONDUTORES
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ABNT
BORDALLO, Caio Cesar Mendes et al. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, v. 64, n. 9, p. 3595-3600, 2017Tradução . . Disponível em: https://doi.org/10.1109/ted.2017.2721110. Acesso em: 06 jul. 2024.
APA
Bordallo, C. C. M., Collaert, N., Claeys, C., Simoen, E., Vandooren, A., Rooyackers, R., et al. (2017). The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, 64( 9), 3595-3600. doi:10.1109/ted.2017.2721110
NLM
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Vancouver
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Trabalho de evento-anais periodico
Study of line-TFET analog performance comparing with other TFET and MOSFET architectures (2017)
Agopian, Paula Ghedini Der ; Simoen, Eddy ; Vandooren, Anne; Rooyackers, Rita; Thean, Aaron; Claeys, Cor ; Martino, João Antonio
Source: Solid-State Electronics Volume 128, February 2017, Pages 43-47. Conference titles: EUROSOI-ULIS 2016. Unidade: EP
Assunto: SEMICONDUTORES
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ABNT
AGOPIAN, Paula Ghedini Der et al. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electronics Volume 128, February 2017, Pages 43-47. [S.l.]: Escola Politécnica, Universidade de São Paulo. Disponível em: https://doi.org/10.1016/j.sse.2016.10.021. Acesso em: 06 jul. 2024. , 2017
APA
Agopian, P. G. D., Simoen, E., Vandooren, A., Rooyackers, R., Thean, A., Claeys, C., & Martino, J. A. (2017). Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electronics Volume 128, February 2017, Pages 43-47. Escola Politécnica, Universidade de São Paulo. doi:10.1016/j.sse.2016.10.021
NLM
Agopian PGD, Simoen E, Vandooren A, Rooyackers R, Thean A, Claeys C, Martino JA. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures [Internet]. Solid-State Electronics Volume 128, February 2017, Pages 43-47. 2017 ; 128 43-47.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1016/j.sse.2016.10.021
Vancouver
Agopian PGD, Simoen E, Vandooren A, Rooyackers R, Thean A, Claeys C, Martino JA. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures [Internet]. Solid-State Electronics Volume 128, February 2017, Pages 43-47. 2017 ; 128 43-47.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1016/j.sse.2016.10.021
Artigo de periodico
Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes (2016)
Oliveira, Alberto Vinicius de; Simoen, Eddy ; Mitard Jerome; Agopian, Paula Ghedini Der ; Langer, Robert; Witters, Liesbeth J; Martino, João Antonio
Source: IEEE Transactions on Electron Devices. Unidade: EP
Subjects: MICROELETRÔNICA, SILÍCIO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Alberto Vinicius de et al. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes. IEEE Transactions on Electron Devices, v. 63, n. 10, p. 4031-4037, 2016Tradução . . Disponível em: https://doi.org/10.1109/ted.2016.2598288. Acesso em: 06 jul. 2024.
APA
Oliveira, A. V. de, Simoen, E., Mitard Jerome,, Agopian, P. G. D., Langer, R., Witters, L. J., & Martino, J. A. (2016). Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes. IEEE Transactions on Electron Devices, 63( 10), 4031-4037. doi:10.1109/ted.2016.2598288
NLM
Oliveira AV de, Simoen E, Mitard Jerome, Agopian PGD, Langer R, Witters LJ, Martino JA. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes [Internet]. IEEE Transactions on Electron Devices. 2016 ; 63( 10): 4031-4037.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/ted.2016.2598288
Vancouver
Oliveira AV de, Simoen E, Mitard Jerome, Agopian PGD, Langer R, Witters LJ, Martino JA. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes [Internet]. IEEE Transactions on Electron Devices. 2016 ; 63( 10): 4031-4037.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1109/ted.2016.2598288
Artigo de periodico
Understanding and optimizing the floating body retention in FDSOI UTBOX (2016)
Aoulaiche, Marc; Bourdelle, K. K.; Witters, Liesbeth J; Caillat, Christian; Simoen, Eddy ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: TRANSISTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
AOULAICHE, Marc et al. Understanding and optimizing the floating body retention in FDSOI UTBOX. Solid-State Electronics, v. 117, p. 123-129, 2016Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2015.11.021. Acesso em: 06 jul. 2024.
APA
Aoulaiche, M., Bourdelle, K. K., Witters, L. J., Caillat, C., Simoen, E., & Martino, J. A. (2016). Understanding and optimizing the floating body retention in FDSOI UTBOX. Solid-State Electronics, 117, 123-129. doi:10.1016/j.sse.2015.11.021
NLM
Aoulaiche M, Bourdelle KK, Witters LJ, Caillat C, Simoen E, Martino JA. Understanding and optimizing the floating body retention in FDSOI UTBOX [Internet]. Solid-State Electronics. 2016 ; 117 123-129.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1016/j.sse.2015.11.021
Vancouver
Aoulaiche M, Bourdelle KK, Witters LJ, Caillat C, Simoen E, Martino JA. Understanding and optimizing the floating body retention in FDSOI UTBOX [Internet]. Solid-State Electronics. 2016 ; 117 123-129.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1016/j.sse.2015.11.021
Artigo de periodico
Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K (2016)
Bordallo, Caio Cesar Mendes ; Vandooren, A; Rooyackers, Rita; Mols, Yannick; Alian, A; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BORDALLO, Caio Cesar Mendes et al. Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K. Semiconductor Science and Technology, v. 31, n. 12, p. 124001, 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/12/124001. Acesso em: 06 jul. 2024.
APA
Bordallo, C. C. M., Vandooren, A., Rooyackers, R., Mols, Y., Alian, A., Agopian, P. G. D., & Martino, J. A. (2016). Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K. Semiconductor Science and Technology, 31( 12), 124001. doi:10.1088/0268-1242/31/12/124001
NLM
Bordallo CCM, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K [Internet]. Semiconductor Science and Technology. 2016 ; 31( 12): 124001.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/0268-1242/31/12/124001
Vancouver
Bordallo CCM, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K [Internet]. Semiconductor Science and Technology. 2016 ; 31( 12): 124001.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/0268-1242/31/12/124001
Artigo de periodico
Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature (2016)
Pavanello, Marcelo Antonio ; Souza, Michelly de; Ribeiro, Thales Augusto; Martino, João Antonio ; Flandre, Denis
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SILÍCIO, SEMICONDUTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature. Semiconductor Science and Technology, v. 31, n. 11, p. 114005, 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/11/114005. Acesso em: 06 jul. 2024.
APA
Pavanello, M. A., Souza, M. de, Ribeiro, T. A., Martino, J. A., & Flandre, D. (2016). Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature. Semiconductor Science and Technology, 31( 11), 114005. doi:10.1088/0268-1242/31/11/114005
NLM
Pavanello MA, Souza M de, Ribeiro TA, Martino JA, Flandre D. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114005.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114005
Vancouver
Pavanello MA, Souza M de, Ribeiro TA, Martino JA, Flandre D. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114005.[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114005
Artigo de periodico
Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes (2016)
Oliveira, Alberto Vinicius de; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Langer, Robert; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Alberto Vinicius de et al. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, v. 31, n. 11, p. 114002 , 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/11/114002. Acesso em: 06 jul. 2024.
APA
Oliveira, A. V. de, Agopian, P. G. D., Simoen, E., Langer, R., Collaert, N., Thean, A., et al. (2016). Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, 31( 11), 114002 . doi:10.1088/0268-1242/31/11/114002
NLM
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002
Vancouver
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 jul. 06 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002

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