Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes (2016)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; AGOPIAN, PAULA GHEDINI DER - EP ; OLIVEIRA, ALBERTO VINICIUS DE - EP
- Unidade: EP
- DOI: 10.1088/0268-1242/31/11/114002
- Subjects: SEMICONDUTORES; MICROELETRÔNICA
- Language: Inglês
- Source:
- Título: Semiconductor Science and Technology
- Volume/Número/Paginação/Ano: v. 31, n. 11, p. 114002 , 2016
- Este artigo possui versão em acesso aberto
- URL de acesso aberto
- Versão do Documento: Versão submetida (Pré-print)
-
Status: Artigo possui versão em acesso aberto em repositório (Green Open Access) -
ABNT
OLIVEIRA, Alberto Vinicius de et al. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, v. 31, n. 11, p. 114002 , 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/11/114002. Acesso em: 11 mar. 2026. -
APA
Oliveira, A. V. de, Agopian, P. G. D., Simoen, E., Langer, R., Collaert, N., Thean, A., et al. (2016). Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, 31( 11), 114002 . doi:10.1088/0268-1242/31/11/114002 -
NLM
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2026 mar. 11 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002 -
Vancouver
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2026 mar. 11 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002 - GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes
- Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes
- Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs
- Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
- Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices
- Experimental Comparison Between Trigate p-TFET and p-FinFET Analog Performance as a Function of Temperature
- Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs
- Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs
- Threshold voltage extraction in Tunnel FETs
- Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source
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