Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs (2016)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; AGOPIAN, PAULA GHEDINI DER - EP ; OLIVEIRA, ALBERTO VINICIUS DE - EP
- Unidade: EP
- DOI: 10.1149/06605.0309ecst
- Subjects: MICROELETRÔNICA; TRANSISTORES
- Language: Inglês
- Source:
- Título: ECS Transactions volume 66 issue 5 on pages 309 to 314
- Volume/Número/Paginação/Ano: v. 66, n. 5, p. 309-314
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
OLIVEIRA, Alberto Vinicius de et al. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314, v. 66, n. 5, p. 309-314, 2016Tradução . . Disponível em: https://doi.org/10.1149/06605.0309ecst. Acesso em: 20 jan. 2026. -
APA
Oliveira, A. V. de, Simoen, E., Thean, A., Agopian, P. G. D., Martino, J. A., Claeys, C., et al. (2016). Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314, 66( 5), 309-314. doi:10.1149/06605.0309ecst -
NLM
Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.[citado 2026 jan. 20 ] Available from: https://doi.org/10.1149/06605.0309ecst -
Vancouver
Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.[citado 2026 jan. 20 ] Available from: https://doi.org/10.1149/06605.0309ecst - Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures
- Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes
- GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes
- Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes
- The impact of the temperature on In0.53Ga0.47As nTFETs
- Study of line-TFET analog performance comparing with other TFET and MOSFET architectures
- Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source
- Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs
- Influence of interface trap density on vertical NW-TFETs with different source composition
- Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices
Informações sobre o DOI: 10.1149/06605.0309ecst (Fonte: oaDOI API)
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