Study of line-TFET analog performance comparing with other TFET and MOSFET architectures (2017)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- DOI: 10.1016/j.sse.2016.10.021
- Assunto: SEMICONDUTORES
- Language: Inglês
- Imprenta:
- Source:
- Título do periódico: Solid-State Electronics Volume 128, February 2017, Pages 43-47
- Volume/Número/Paginação/Ano: v. 128, p. 43-47, Fev 2017
- Este periódico é de assinatura
- Este artigo é de acesso aberto
- URL de acesso aberto
- Cor do Acesso Aberto: green
-
ABNT
AGOPIAN, Paula Ghedini Der; COLLAERT, N; ALIAN, A; et al. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electronics Volume 128, February 2017, Pages 43-47[S.l.], Elsevier, v. 128, p. 43-47, 2017. Disponível em: < https://doi.org/10.1016/j.sse.2016.10.021 > DOI: 10.1016/j.sse.2016.10.021. -
APA
Agopian, P. G. D., Collaert, N., Alian, A., Simoen, E., Claeys, C., & Martino, J. A. (2017). Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electronics Volume 128, February 2017, Pages 43-47, 128, 43-47. doi:10.1016/j.sse.2016.10.021 -
NLM
Agopian PGD, Collaert N, Alian A, Simoen E, Claeys C, Martino JA. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures [Internet]. Solid-State Electronics Volume 128, February 2017, Pages 43-47. 2017 ; 128 43-47.Available from: https://doi.org/10.1016/j.sse.2016.10.021 -
Vancouver
Agopian PGD, Collaert N, Alian A, Simoen E, Claeys C, Martino JA. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures [Internet]. Solid-State Electronics Volume 128, February 2017, Pages 43-47. 2017 ; 128 43-47.Available from: https://doi.org/10.1016/j.sse.2016.10.021 - Low-Frequency noise behaviour of bulk and DTMOS triple-gate devices under 60 MeV proton irradiaton
- Extraction of the oxide charge density at front and back interfaces of SOI NMOSFET devices
- Components of the leakage current in enhancement-mode SOI nMOSFETs at high temperature. (em CD-Rom)
- A new method for determination of the oxide charge density at the buried oxide/substrate interface in SOI capacitor
- A novel leakage drain current model for SOI MOSFETs devices at high temperature
- A physically-based continuous model for graded-channel SOI MOSFET
- Transistor soi-nmosfet nao auto-alinhado
- Metodo simples para a obtencao da densidade de armadilhas na primeira e segunda interface em soi-mosfet
- Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k
- Influencia da temperatura em transistores soi (silicon on insulator) mosfets
Informações sobre o DOI: 10.1016/j.sse.2016.10.021 (Fonte: oaDOI API)
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