Performance of differential pair circuits designed with line tunnel FET devices at different temperatures (2018)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; AGOPIAN, PAULA GHEDINI DER - EP ; MARTINO, MARCIO DALLA VALLE - EP
- Unidade: EP
- DOI: 10.1088/1361-6641/aac4fd
- Assunto: SEMICONDUTORES
- Language: Inglês
- Source:
- Título: Semiconductor Science and Technology
- ISSN: 1361-6641
- Volume/Número/Paginação/Ano: v. 33, n. 7, p. 075012, 2018
- Este periódico é de assinatura
- Este artigo é de acesso aberto
- URL de acesso aberto
- Cor do Acesso Aberto: green
- Licença: other-oa
-
ABNT
MARTINO, Márcio Dalla Valle et al. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, v. 33, n. 7, p. 075012, 2018Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/aac4fd. Acesso em: 03 dez. 2025. -
APA
Martino, M. D. V., Claeys, C., Agopian, P. G. D., Rooyackers, R., Simoen, E., & Martino, J. A. (2018). Performance of differential pair circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, 33( 7), 075012. doi:10.1088/1361-6641/aac4fd -
NLM
Martino MDV, Claeys C, Agopian PGD, Rooyackers R, Simoen E, Martino JA. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2018 ; 33( 7): 075012.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1088/1361-6641/aac4fd -
Vancouver
Martino MDV, Claeys C, Agopian PGD, Rooyackers R, Simoen E, Martino JA. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2018 ; 33( 7): 075012.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1088/1361-6641/aac4fd - Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures
- Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism
- Nanowire Tunnel Field Effect Transistors at High Temperature
- Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures
- Cross-section features influence on surrounding MuGFETs
- Threshold voltage extraction in Tunnel FETs
- Influence of interface trap density on vertical NW-TFETs with different source composition
- Temperature influence on nanowire tunnel field effect transistors
- The impact of the temperature on In0.53Ga0.47As nTFETs
- Study of line-TFET analog performance comparing with other TFET and MOSFET architectures
Informações sobre o DOI: 10.1088/1361-6641/aac4fd (Fonte: oaDOI API)
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