Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures (2016)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; AGOPIAN, PAULA GHEDINI DER - EP ; MARTINO, MARCIO DALLA VALLE - EP
- Unidade: EP
- DOI: 10.1088/0268-1242/31/5/055001
- Assunto: SEMICONDUTORES
- Language: Inglês
- Source:
- Título: Semiconductor Science and Technology
- Volume/Número/Paginação/Ano: v. 31, n. 5, 055001, 2016
- Status:
- Artigo possui versão em acesso aberto em repositório (Green Open Access)
- Versão do Documento:
- Versão submetida (Pré-print)
- Acessar versão aberta:
-
ABNT
MARTINO, Márcio Dalla Valle et al. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures. Semiconductor Science and Technology, v. 31, n. 5, 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/5/055001. Acesso em: 24 mar. 2026. -
APA
Martino, M. D. V., Martino, J. A., Agopian, P. G. D., Vandooren, A., Rooyackers, R., Simoen, E., & Claeys, C. (2016). Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures. Semiconductor Science and Technology, 31( 5). doi:10.1088/0268-1242/31/5/055001 -
NLM
Martino MDV, Martino JA, Agopian PGD, Vandooren A, Rooyackers R, Simoen E, Claeys C. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures [Internet]. Semiconductor Science and Technology. 2016 ; 31( 5):[citado 2026 mar. 24 ] Available from: https://doi.org/10.1088/0268-1242/31/5/055001 -
Vancouver
Martino MDV, Martino JA, Agopian PGD, Vandooren A, Rooyackers R, Simoen E, Claeys C. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures [Internet]. Semiconductor Science and Technology. 2016 ; 31( 5):[citado 2026 mar. 24 ] Available from: https://doi.org/10.1088/0268-1242/31/5/055001 - Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures
- Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism
- Performance of differential pair circuits designed with line tunnel FET devices at different temperatures
- Nanowire Tunnel Field Effect Transistors at High Temperature
- Cross-section features influence on surrounding MuGFETs
- Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices
- Experimental Comparison Between Trigate p-TFET and p-FinFET Analog Performance as a Function of Temperature
- Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs
- Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs
- Threshold voltage extraction in Tunnel FETs
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