Nanowire Tunnel Field Effect Transistors at High Temperature (2013)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; AGOPIAN, PAULA GHEDINI DER - EP ; MARTINO, MARCIO DALLA VALLE - EP
- Unidade: EP
- DOI: 10.29292/jics.v8i2.381
- Assunto: NANOELETRÔNICA
- Language: Inglês
- Source:
- Título: Journal of Integrated Circuits and Systems
- Volume/Número/Paginação/Ano: v.8, n.2, p. 110-115, 2013
- Status:
- Artigo publicado em periódico de acesso aberto (Gold Open Access)
- Versão do Documento:
- Versão publicada (Published version)
- Acessar versão aberta:
-
ABNT
MARTINO, Márcio Dalla Valle et al. Nanowire Tunnel Field Effect Transistors at High Temperature. Journal of Integrated Circuits and Systems, v. 8, n. 2, p. 110-115, 2013Tradução . . Disponível em: https://doi.org/10.29292/jics.v8i2.381. Acesso em: 24 mar. 2026. -
APA
Martino, M. D. V., Neves, F. S., Agopian, P. G. D., Martino, J. A., Rooyackers, R., & Claeys, C. (2013). Nanowire Tunnel Field Effect Transistors at High Temperature. Journal of Integrated Circuits and Systems, 8( 2), 110-115. doi:10.29292/jics.v8i2.381 -
NLM
Martino MDV, Neves FS, Agopian PGD, Martino JA, Rooyackers R, Claeys C. Nanowire Tunnel Field Effect Transistors at High Temperature [Internet]. Journal of Integrated Circuits and Systems. 2013 ;8( 2): 110-115.[citado 2026 mar. 24 ] Available from: https://doi.org/10.29292/jics.v8i2.381 -
Vancouver
Martino MDV, Neves FS, Agopian PGD, Martino JA, Rooyackers R, Claeys C. Nanowire Tunnel Field Effect Transistors at High Temperature [Internet]. Journal of Integrated Circuits and Systems. 2013 ;8( 2): 110-115.[citado 2026 mar. 24 ] Available from: https://doi.org/10.29292/jics.v8i2.381 - Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures
- Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures
- Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism
- Performance of differential pair circuits designed with line tunnel FET devices at different temperatures
- Cross-section features influence on surrounding MuGFETs
- Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices
- Experimental Comparison Between Trigate p-TFET and p-FinFET Analog Performance as a Function of Temperature
- Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs
- Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs
- Threshold voltage extraction in Tunnel FETs
Informações sobre a disponibilidade de versões do artigo em acesso aberto coletadas automaticamente via oaDOI API (Unpaywall).
Por se tratar de integração com serviço externo, podem existir diferentes versões do trabalho (como preprints ou postprints), que podem diferir da versão publicada.
How to cite
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
