Nanowire Tunnel Field Effect Transistors at High Temperature (2013)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; AGOPIAN, PAULA GHEDINI DER - EP ; MARTINO, MARCIO DALLA VALLE - EP
- Unidade: EP
- DOI: 10.29292/jics.v8i2.381
- Assunto: NANOELETRÔNICA
- Language: Inglês
- Source:
- Título: Journal of Integrated Circuits and Systems
- Volume/Número/Paginação/Ano: v.8, n.2, p. 110-115, 2013
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
MARTINO, Márcio Dalla Valle et al. Nanowire Tunnel Field Effect Transistors at High Temperature. Journal of Integrated Circuits and Systems, v. 8, n. 2, p. 110-115, 2013Tradução . . Disponível em: https://doi.org/10.29292/jics.v8i2.381. Acesso em: 21 jan. 2026. -
APA
Martino, M. D. V., Neves, F. S., Agopian, P. G. D., Martino, J. A., Rooyackers, R., & Claeys, C. (2013). Nanowire Tunnel Field Effect Transistors at High Temperature. Journal of Integrated Circuits and Systems, 8( 2), 110-115. doi:10.29292/jics.v8i2.381 -
NLM
Martino MDV, Neves FS, Agopian PGD, Martino JA, Rooyackers R, Claeys C. Nanowire Tunnel Field Effect Transistors at High Temperature [Internet]. Journal of Integrated Circuits and Systems. 2013 ;8( 2): 110-115.[citado 2026 jan. 21 ] Available from: https://doi.org/10.29292/jics.v8i2.381 -
Vancouver
Martino MDV, Neves FS, Agopian PGD, Martino JA, Rooyackers R, Claeys C. Nanowire Tunnel Field Effect Transistors at High Temperature [Internet]. Journal of Integrated Circuits and Systems. 2013 ;8( 2): 110-115.[citado 2026 jan. 21 ] Available from: https://doi.org/10.29292/jics.v8i2.381 - Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism
- Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures
- Performance of differential pair circuits designed with line tunnel FET devices at different temperatures
- Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures
- Cross-section features influence on surrounding MuGFETs
- The impact of the temperature on In0.53Ga0.47As nTFETs
- Study of line-TFET analog performance comparing with other TFET and MOSFET architectures
- Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source
- Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs
- Influence of interface trap density on vertical NW-TFETs with different source composition
Informações sobre o DOI: 10.29292/jics.v8i2.381 (Fonte: oaDOI API)
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