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Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET (2023)
Ramos, Daniel Augusto; Sasaki, Kátia Regina Akemi ; Rangel, Ricardo Cardoso; Duarte, Pedro Henrique; Martino, João Antonio
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices. Unidade: EP
Subjects: DISPOSITIVOS ELETRÔNICOS, TRANSISTORES, MICROELETRÔNICA
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ABNT
RAMOS, Daniel Augusto et al. Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET. 2023, Anais.. [Piscataway, N.J.]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302644. Acesso em: 13 nov. 2024.
APA
Ramos, D. A., Sasaki, K. R. A., Rangel, R. C., Duarte, P. H., & Martino, J. A. (2023). Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET. In SBMicro. [Piscataway, N.J.]: IEEE. doi:10.1109/SBMicro60499.2023.10302644
NLM
Ramos DA, Sasaki KRA, Rangel RC, Duarte PH, Martino JA. Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET [Internet]. SBMicro. 2023 ;[citado 2024 nov. 13 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302644
Vancouver
Ramos DA, Sasaki KRA, Rangel RC, Duarte PH, Martino JA. Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET [Internet]. SBMicro. 2023 ;[citado 2024 nov. 13 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302644
Artigo de periodico
The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs (2017)
Bordallo, Caio Cesar Mendes ; Collaert, Nadine ; Claeys, Cor ; Simoen, Eddy ; Vandooren, A; Rooyackers, Rita; Mols, Yannick; Alian, A; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: IEEE Transactions on Electron Devices. Unidade: EP
Subjects: MICROELETRÔNICA, SEMICONDUTORES
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ABNT
BORDALLO, Caio Cesar Mendes et al. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, v. 64, n. 9, p. 3595-3600, 2017Tradução . . Disponível em: https://doi.org/10.1109/ted.2017.2721110. Acesso em: 13 nov. 2024.
APA
Bordallo, C. C. M., Collaert, N., Claeys, C., Simoen, E., Vandooren, A., Rooyackers, R., et al. (2017). The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, 64( 9), 3595-3600. doi:10.1109/ted.2017.2721110
NLM
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Vancouver
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Artigo de periodico
Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes (2016)
Oliveira, Alberto Vinicius de; Simoen, Eddy ; Mitard Jerome; Agopian, Paula Ghedini Der ; Langer, Robert; Witters, Liesbeth J; Martino, João Antonio
Source: IEEE Transactions on Electron Devices. Unidade: EP
Subjects: MICROELETRÔNICA, SILÍCIO
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes. IEEE Transactions on Electron Devices, v. 63, n. 10, p. 4031-4037, 2016Tradução . . Disponível em: https://doi.org/10.1109/ted.2016.2598288. Acesso em: 13 nov. 2024.
APA
Oliveira, A. V. de, Simoen, E., Mitard Jerome,, Agopian, P. G. D., Langer, R., Witters, L. J., & Martino, J. A. (2016). Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes. IEEE Transactions on Electron Devices, 63( 10), 4031-4037. doi:10.1109/ted.2016.2598288
NLM
Oliveira AV de, Simoen E, Mitard Jerome, Agopian PGD, Langer R, Witters LJ, Martino JA. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes [Internet]. IEEE Transactions on Electron Devices. 2016 ; 63( 10): 4031-4037.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1109/ted.2016.2598288
Vancouver
Oliveira AV de, Simoen E, Mitard Jerome, Agopian PGD, Langer R, Witters LJ, Martino JA. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes [Internet]. IEEE Transactions on Electron Devices. 2016 ; 63( 10): 4031-4037.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1109/ted.2016.2598288
Artigo de periodico
Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K (2016)
Bordallo, Caio Cesar Mendes ; Vandooren, A; Rooyackers, Rita; Mols, Yannick; Alian, A; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
BORDALLO, Caio Cesar Mendes et al. Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K. Semiconductor Science and Technology, v. 31, n. 12, p. 124001, 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/12/124001. Acesso em: 13 nov. 2024.
APA
Bordallo, C. C. M., Vandooren, A., Rooyackers, R., Mols, Y., Alian, A., Agopian, P. G. D., & Martino, J. A. (2016). Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K. Semiconductor Science and Technology, 31( 12), 124001. doi:10.1088/0268-1242/31/12/124001
NLM
Bordallo CCM, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K [Internet]. Semiconductor Science and Technology. 2016 ; 31( 12): 124001.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1088/0268-1242/31/12/124001
Vancouver
Bordallo CCM, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K [Internet]. Semiconductor Science and Technology. 2016 ; 31( 12): 124001.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1088/0268-1242/31/12/124001
Artigo de periodico
Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes (2016)
Oliveira, Alberto Vinicius de; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Langer, Robert; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, v. 31, n. 11, p. 114002 , 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/11/114002. Acesso em: 13 nov. 2024.
APA
Oliveira, A. V. de, Agopian, P. G. D., Simoen, E., Langer, R., Collaert, N., Thean, A., et al. (2016). Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, 31( 11), 114002 . doi:10.1088/0268-1242/31/11/114002
NLM
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 nov. 13 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002
Vancouver
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 nov. 13 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002
Artigo de periodico
Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs (2016)
Oliveira, Alberto Vinicius de; Simoen, Eddy ; Thean, Aaron; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Claeys, Cor ; Mertens, Hans; Collaert, Nadine
Source: ECS Transactions volume 66 issue 5 on pages 309 to 314. Unidade: EP
Subjects: MICROELETRÔNICA, TRANSISTORES
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314, v. 66, n. 5, p. 309-314, 2016Tradução . . Disponível em: https://doi.org/10.1149/06605.0309ecst. Acesso em: 13 nov. 2024.
APA
Oliveira, A. V. de, Simoen, E., Thean, A., Agopian, P. G. D., Martino, J. A., Claeys, C., et al. (2016). Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314, 66( 5), 309-314. doi:10.1149/06605.0309ecst
NLM
Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1149/06605.0309ecst
Vancouver
Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1149/06605.0309ecst
Artigo de periodico
Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures (2016)
Oliveira, Alberto Vinicius de; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Simoen, Eddy ; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, v. 123, p. 124-129, 2016Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2016.05.004. Acesso em: 13 nov. 2024.
APA
Oliveira, A. V. de, Collaert, N., Thean, A., Claeys, C., Simoen, E., Agopian, P. G. D., & Martino, J. A. (2016). Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, 123, 124-129. doi:10.1016/j.sse.2016.05.004
NLM
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004
Vancouver
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004
Artigo de periodico
InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature (2016)
Alian, A; Agopian, Paula Ghedini Der ; Verhulist, A.; Verreck, D.; Bordallo, Caio Cesar Mendes ; Martino, João Antonio ; Alian1, Y. Mols1, C. C. M. Bordallo2, D. Verreck3, A. Verhulst1, A. Vandooren1, R. Rooyackers1, P. G. D. Agopian2,4, J. A. Martino2, A. Thean1,a), D. Lin1, D. Mocuta1, and N. Collaert1
Source: Applied Physics Letters. Unidade: EP
Subjects: NANOTECNOLOGIA, MICROELETRÔNICA
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ABNT
ALIAN, A et al. InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature. Applied Physics Letters, v. 109, n. 24, p. 243502, 2016Tradução . . Disponível em: https://doi.org/10.1063/1.4971830. Acesso em: 13 nov. 2024.
APA
Alian, A., Agopian, P. G. D., Verhulist, A., Verreck, D., Bordallo, C. C. M., Martino, J. A., & Alian1, Y. M. 1. (2016). InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature. Applied Physics Letters, 109( 24), 243502. doi:10.1063/1.4971830
NLM
Alian A, Agopian PGD, Verhulist A, Verreck D, Bordallo CCM, Martino JA, Alian1 YM1. InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature [Internet]. Applied Physics Letters. 2016 ; 109( 24): 243502.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1063/1.4971830
Vancouver
Alian A, Agopian PGD, Verhulist A, Verreck D, Bordallo CCM, Martino JA, Alian1 YM1. InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature [Internet]. Applied Physics Letters. 2016 ; 109( 24): 243502.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1063/1.4971830
Artigo de periodico
Enhanced dynamic threshold voltage UTBB SOI nMOSFETs (2015)
Sasaki, Kátia Regina Akemi; Manini, Matheus Barros; Claeys, Cor ; Simoen, Eddy ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
SASAKI, Kátia Regina Akemi et al. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. Solid-State Electronics, v. 112, p. 19-23, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2015.02.011. Acesso em: 13 nov. 2024.
APA
Sasaki, K. R. A., Manini, M. B., Claeys, C., Simoen, E., & Martino, J. A. (2015). Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. Solid-State Electronics, 112, 19-23. doi:10.1016/j.sse.2015.02.011
NLM
Sasaki KRA, Manini MB, Claeys C, Simoen E, Martino JA. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs [Internet]. Solid-State Electronics. 2015 ; 112 19-23.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2015.02.011
Vancouver
Sasaki KRA, Manini MB, Claeys C, Simoen E, Martino JA. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs [Internet]. Solid-State Electronics. 2015 ; 112 19-23.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2015.02.011
Artigo de periodico
Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View (2015)
Sasaki, Kátia Regina Akemi; Aoulaiche, Marc; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: J. Low Power Electron. Appl. 2015, 5(2), 69-80. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SASAKI, Kátia Regina Akemi et al. Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View. J. Low Power Electron. Appl. 2015, 5(2), 69-80, v. 5, n. 2, p. 69-80, 2015Tradução . . Disponível em: https://doi.org/10.3390/jlpea5020069. Acesso em: 13 nov. 2024.
APA
Sasaki, K. R. A., Aoulaiche, M., Simoen, E., Claeys, C., & Martino, J. A. (2015). Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View. J. Low Power Electron. Appl. 2015, 5(2), 69-80, 5( 2), 69-80. doi:10.3390/jlpea5020069
NLM
Sasaki KRA, Aoulaiche M, Simoen E, Claeys C, Martino JA. Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View [Internet]. J. Low Power Electron. Appl. 2015, 5(2), 69-80. 2015 ; 5( 2): 69-80.[citado 2024 nov. 13 ] Available from: https://doi.org/10.3390/jlpea5020069
Vancouver
Sasaki KRA, Aoulaiche M, Simoen E, Claeys C, Martino JA. Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View [Internet]. J. Low Power Electron. Appl. 2015, 5(2), 69-80. 2015 ; 5( 2): 69-80.[citado 2024 nov. 13 ] Available from: https://doi.org/10.3390/jlpea5020069
Artigo de periodico
In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs (2015)
Doria, Rodrigo Trevisoli ; Claeys, Cor ; Simoen, Eddy ; Souza, Marcio Alves Sodré de; Martino, João Antonio
Source: Microelectronic Engineering. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
DORIA, Rodrigo Trevisoli et al. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, v. 147, n. 1, p. 92-95, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.mee.2015.04.056. Acesso em: 13 nov. 2024.
APA
Doria, R. T., Claeys, C., Simoen, E., Souza, M. A. S. de, & Martino, J. A. (2015). In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, 147( 1), 92-95. doi:10.1016/j.mee.2015.04.056
NLM
Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.mee.2015.04.056
Vancouver
Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.mee.2015.04.056
Artigo de periodico
Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs (2015)
Bühler, Rudolf Theoderich; Agopian, Paula Ghedini Der ; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
BÜHLER, Rudolf Theoderich et al. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, v. 103, p. 209-215, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.07.010. Acesso em: 13 nov. 2024.
APA
Bühler, R. T., Agopian, P. G. D., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2015). Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, 103, 209-215. doi:10.1016/j.sse.2014.07.010
NLM
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Vancouver
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Artigo de periodico
Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs (2015)
Agopian, Paula Ghedini Der ; Martino, João Antonio ; Santos, Sara Dereste dos; Rooyackers, Rita; Vandoren, A
Source: IEEE Transactions on Electron Devices. Unidade: EP
Subjects: MICROELETRÔNICA, TRANSISTORES, SILÍCIO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
AGOPIAN, Paula Ghedini Der et al. Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs. IEEE Transactions on Electron Devices, v. 62, n. Ja 2015, p. 16-22, 2015Tradução . . Disponível em: https://doi.org/10.1109/ted.2014.2367659. Acesso em: 13 nov. 2024.
APA
Agopian, P. G. D., Martino, J. A., Santos, S. D. dos, Rooyackers, R., & Vandoren, A. (2015). Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs. IEEE Transactions on Electron Devices, 62( Ja 2015), 16-22. doi:10.1109/ted.2014.2367659
NLM
Agopian PGD, Martino JA, Santos SD dos, Rooyackers R, Vandoren A. Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs [Internet]. IEEE Transactions on Electron Devices. 2015 ; 62( Ja 2015): 16-22.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1109/ted.2014.2367659
Vancouver
Agopian PGD, Martino JA, Santos SD dos, Rooyackers R, Vandoren A. Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs [Internet]. IEEE Transactions on Electron Devices. 2015 ; 62( Ja 2015): 16-22.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1109/ted.2014.2367659
Artigo de periodico
Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism (2015)
Martino, Márcio Dalla Valle; Thean, Aaron; Claeys, Cor ; Neves, Felipe S; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Vandooren, A; Rooyackers, Rita; Simoen, Eddy
Source: Solid-State Electronics. Unidade: EP
Subjects: TRANSISTORES, MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARTINO, Márcio Dalla Valle et al. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism. Solid-State Electronics, v. 112, p. 51-55, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2015.02.006. Acesso em: 13 nov. 2024.
APA
Martino, M. D. V., Thean, A., Claeys, C., Neves, F. S., Agopian, P. G. D., Martino, J. A., et al. (2015). Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism. Solid-State Electronics, 112, 51-55. doi:10.1016/j.sse.2015.02.006
NLM
Martino MDV, Thean A, Claeys C, Neves FS, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism [Internet]. Solid-State Electronics. 2015 ; 112 51-55.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2015.02.006
Vancouver
Martino MDV, Thean A, Claeys C, Neves FS, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism [Internet]. Solid-State Electronics. 2015 ; 112 51-55.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2015.02.006
Artigo de periodico
Threshold voltage extraction in Tunnel FETs (2014)
Ortiz-Conde, Adelmo; Martino, João Antonio ; Garcia- Sanchez, Francisco J.; Muci, Juan; Martino, João Antonio ; Agopian, Paula Ghedini Der ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ORTIZ-CONDE, Adelmo et al. Threshold voltage extraction in Tunnel FETs. Solid-State Electronics, v. 93, p. 49-55, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.12.010. Acesso em: 13 nov. 2024.
APA
Ortiz-Conde, A., Martino, J. A., Garcia- Sanchez, F. J., Muci, J., Martino, J. A., Agopian, P. G. D., & Claeys, C. (2014). Threshold voltage extraction in Tunnel FETs. Solid-State Electronics, 93, 49-55. doi:10.1016/j.sse.2013.12.010
NLM
Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2013.12.010
Vancouver
Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2013.12.010
Artigo de periodico
Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation (2014)
Caño de Andrade, Maria Glória; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Aoulaiche, Marc; Martino, João Antonio
Source: Microelectronics Reliability. Unidade: EP
Subjects: SILÍCIO, MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CAÑO DE ANDRADE, Maria Glória et al. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability, v. 54, n. 11, p. 2349-2354, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.microrel.2014.06.013. Acesso em: 13 nov. 2024.
APA
Caño de Andrade, M. G., Collaert, N., Simoen, E., Claeys, C., Aoulaiche, M., & Martino, J. A. (2014). Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability, 54( 11), 2349-2354. doi:10.1016/j.microrel.2014.06.013
NLM
Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.microrel.2014.06.013
Vancouver
Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.microrel.2014.06.013
Artigo de periodico
Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs (2014)
Teixeira, Fernando Ferrari; Martino, João Antonio ; Bordallo, Caio Cesar Mendes ; Silveira, Marcilei Aparecida Guazzelli da; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Claeys, Cor
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Subjects: MICROELETRÔNICA, RAIOS X
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
TEIXEIRA, Fernando Ferrari et al. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs. Journal of Integrated Circuits and Systems, v. 9, n. 2, p. 97-102, 2014Tradução . . Disponível em: https://doi.org/10.29292/jics.v9i2.394. Acesso em: 13 nov. 2024.
APA
Teixeira, F. F., Martino, J. A., Bordallo, C. C. M., Silveira, M. A. G. da, Agopian, P. G. D., Simoen, E., & Claeys, C. (2014). Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs. Journal of Integrated Circuits and Systems, 9( 2), 97-102. doi:10.29292/jics.v9i2.394
NLM
Teixeira FF, Martino JA, Bordallo CCM, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 97-102.[citado 2024 nov. 13 ] Available from: https://doi.org/10.29292/jics.v9i2.394
Vancouver
Teixeira FF, Martino JA, Bordallo CCM, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 97-102.[citado 2024 nov. 13 ] Available from: https://doi.org/10.29292/jics.v9i2.394
Artigo de periodico
Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation (2014)
Bordallo, Caio Cesar Mendes ; Martino, João Antonio ; Teixeira, Fernando Ferrari; Silveira, Marcilei Aparecida Guazzelli da; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Claeys, Cor
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: RAIOS X, MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BORDALLO, Caio Cesar Mendes et al. Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation. Semiconductor Science and Technology, v. 29, n. 12, p. 125015, 2014Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/29/12/125015. Acesso em: 13 nov. 2024.
APA
Bordallo, C. C. M., Martino, J. A., Teixeira, F. F., Silveira, M. A. G. da, Agopian, P. G. D., Simoen, E., & Claeys, C. (2014). Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation. Semiconductor Science and Technology, 29( 12), 125015. doi:10.1088/0268-1242/29/12/125015
NLM
Bordallo CCM, Martino JA, Teixeira FF, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation [Internet]. Semiconductor Science and Technology. 2014 ; 29( 12): 125015.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1088/0268-1242/29/12/125015
Vancouver
Bordallo CCM, Martino JA, Teixeira FF, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation [Internet]. Semiconductor Science and Technology. 2014 ; 29( 12): 125015.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1088/0268-1242/29/12/125015
Artigo de periodico
Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation (2014)
Nicoletti, Talitha; Santos, Sara Dereste dos; Martino, João Antonio ; Aoulaiche, Marc; Veloso, Anabela; Claeys, Cor ; Simoen, Eddy ; Jurczak, Malgorzata
Source: Solid-State Electronics. Unidade: EP
Subjects: TEMPERATURA, MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETTI, Talitha et al. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, v. 91, p. 53-58, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.09.012. Acesso em: 13 nov. 2024.
APA
Nicoletti, T., Santos, S. D. dos, Martino, J. A., Aoulaiche, M., Veloso, A., Claeys, C., et al. (2014). Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, 91, 53-58. doi:10.1016/j.sse.2013.09.012
NLM
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Vancouver
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Artigo de periodico
Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results (2014)
Nissimoff, Albert; Claeys, Cor ; Aoulaiche, Marc; Sasaki, Karen Lucia Mayumi; Simoen, Eddy ; Martino, João Antonio
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NISSIMOFF, Albert et al. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, v. 9, n. 2, p. 91-96, 2014Tradução . . Disponível em: https://doi.org/10.29292/jics.v9i2.393. Acesso em: 13 nov. 2024.
APA
Nissimoff, A., Claeys, C., Aoulaiche, M., Sasaki, K. L. M., Simoen, E., & Martino, J. A. (2014). Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, 9( 2), 91-96. doi:10.29292/jics.v9i2.393
NLM
Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2024 nov. 13 ] Available from: https://doi.org/10.29292/jics.v9i2.393
Vancouver
Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2024 nov. 13 ] Available from: https://doi.org/10.29292/jics.v9i2.393

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