Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results (2014)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- DOI: 10.29292/jics.v9i2.393
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Source:
- Título: Journal of Integrated Circuits and Systems
- Volume/Número/Paginação/Ano: v. 9, n. 2, p. 91-96, Jan 2014
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
NISSIMOFF, Albert et al. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, v. 9, n. 2, p. 91-96, 2014Tradução . . Disponível em: https://doi.org/10.29292/jics.v9i2.393. Acesso em: 23 jan. 2026. -
APA
Nissimoff, A., Claeys, C., Aoulaiche, M., Sasaki, K. L. M., Simoen, E., & Martino, J. A. (2014). Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, 9( 2), 91-96. doi:10.29292/jics.v9i2.393 -
NLM
Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2026 jan. 23 ] Available from: https://doi.org/10.29292/jics.v9i2.393 -
Vancouver
Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2026 jan. 23 ] Available from: https://doi.org/10.29292/jics.v9i2.393 - Analog circuit design using graded-channel SOI NMOSFETs
- Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures
- Extraction of the interface and oxide charge density in silicon-on-insulator MOSFETs
- Projeto de um processo CMOS com cavidade dupla e dimensões de porta de 2 um
- Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
- Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation
- Estudo comparativo de estruturas de fonte e dreno de transistores mos submicrometricos
- Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices
- Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs
- Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs
Informações sobre o DOI: 10.29292/jics.v9i2.393 (Fonte: oaDOI API)
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