Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs (2000)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher: IEEE/SBC
- Publisher place: Piscataway
- Date published: 2000
- Source:
- Título: LATW 00: proceedings
- Conference titles: IEEE Latin American Test Workshop
-
ABNT
PAVANELLO, Marcelo Antonio e NICOLETT, Aparecido Sirley e MARTINO, João Antonio. Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs. 2000, Anais.. Piscataway: IEEE/SBC, 2000. . Acesso em: 23 jan. 2026. -
APA
Pavanello, M. A., Nicolett, A. S., & Martino, J. A. (2000). Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs. In LATW 00: proceedings. Piscataway: IEEE/SBC. -
NLM
Pavanello MA, Nicolett AS, Martino JA. Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs. LATW 00: proceedings. 2000 ;[citado 2026 jan. 23 ] -
Vancouver
Pavanello MA, Nicolett AS, Martino JA. Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs. LATW 00: proceedings. 2000 ;[citado 2026 jan. 23 ] - Analog circuit design using graded-channel SOI NMOSFETs
- Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures
- Extraction of the interface and oxide charge density in silicon-on-insulator MOSFETs
- Projeto de um processo CMOS com cavidade dupla e dimensões de porta de 2 um
- Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
- Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation
- Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results
- Estudo comparativo de estruturas de fonte e dreno de transistores mos submicrometricos
- Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices
- Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs
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