Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs (2000)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher: IEEE/SBC
- Publisher place: Piscataway
- Date published: 2000
- Source:
- Título: LATW 00: proceedings
- Conference titles: IEEE Latin American Test Workshop
-
ABNT
PAVANELLO, Marcelo Antonio e NICOLETT, Aparecido Sirley e MARTINO, João Antonio. Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs. 2000, Anais.. Piscataway: IEEE/SBC, 2000. . Acesso em: 15 mar. 2026. -
APA
Pavanello, M. A., Nicolett, A. S., & Martino, J. A. (2000). Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs. In LATW 00: proceedings. Piscataway: IEEE/SBC. -
NLM
Pavanello MA, Nicolett AS, Martino JA. Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs. LATW 00: proceedings. 2000 ;[citado 2026 mar. 15 ] -
Vancouver
Pavanello MA, Nicolett AS, Martino JA. Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs. LATW 00: proceedings. 2000 ;[citado 2026 mar. 15 ] - Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance
- Caracterização elétrica de dispositivos SOI MOS em baixa temperatura
- Metodo simples para a obtencao da densidade de armadilhas na primeira e segunda interface em soi-mosfet
- Combined l and series resistance extraction of ldd mosfets
- Influencia da temperatura em transistores soi (silicon on insulator) mosfets
- Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k
- The impact of gate length scaling on UTBOX FDSOI devices: the digital/analog performance of extension-less structures
- Simple method for the determination of the interface trap density at 77k in fully depleted acumulation mode soi mosfets
- Transistor soi-nmosfet nao auto-alinhado
- Impact of selective epitaxial growth and uniaxial/biaxial strain on DIBL effect using triple gate FinFETs
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