Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices (2012)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- DOI: 10.1109/ULIS.2012.6193357
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher: IEEE
- Publisher place: Piscataway
- Date published: 2012
- Source:
- Título: Proceedings of the conference
- Conference titles: International Conference on Ultimate Integration on Silicon
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
ALMEIDA, Luciano Mendes et al. Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices. 2012, Anais.. Piscataway: IEEE, 2012. Disponível em: https://doi.org/10.1109/ULIS.2012.6193357. Acesso em: 23 jan. 2026. -
APA
Almeida, L. M., Martino, J. A., Aoulaiche, M., Sasaki, K. R. A., Nicoletti, T., Collaert, N., et al. (2012). Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices. In Proceedings of the conference. Piscataway: IEEE. doi:10.1109/ULIS.2012.6193357 -
NLM
Almeida LM, Martino JA, Aoulaiche M, Sasaki KRA, Nicoletti T, Collaert N, Simoen E, Claeys C, Jurczak MJ. Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices [Internet]. Proceedings of the conference. 2012 ;[citado 2026 jan. 23 ] Available from: https://doi.org/10.1109/ULIS.2012.6193357 -
Vancouver
Almeida LM, Martino JA, Aoulaiche M, Sasaki KRA, Nicoletti T, Collaert N, Simoen E, Claeys C, Jurczak MJ. Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices [Internet]. Proceedings of the conference. 2012 ;[citado 2026 jan. 23 ] Available from: https://doi.org/10.1109/ULIS.2012.6193357 - Analog circuit design using graded-channel SOI NMOSFETs
- Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures
- Extraction of the interface and oxide charge density in silicon-on-insulator MOSFETs
- Projeto de um processo CMOS com cavidade dupla e dimensões de porta de 2 um
- Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
- Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation
- Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results
- Estudo comparativo de estruturas de fonte e dreno de transistores mos submicrometricos
- Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs
- Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs
Informações sobre o DOI: 10.1109/ULIS.2012.6193357 (Fonte: oaDOI API)
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