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Trabalho de evento
Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements (2012)
Mariniello, Genaro ; Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
MARINIELLO, Genaro et al. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0231ecst. Acesso em: 02 nov. 2024.
APA
Mariniello, G., Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0231ecst
NLM
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0231ecst
Vancouver
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0231ecst
Trabalho de evento
Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime (2012)
Souza, Marcio Alves Sodré de; Doria, Rodrigo Trevisoli ; Souza, Michelly de ; Martino, João Antonio ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SOUZA, Marcio Alves Sodré de et al. Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0077ecst. Acesso em: 02 nov. 2024.
APA
Souza, M. A. S. de, Doria, R. T., Souza, M. de, Martino, J. A., & Pavanello, M. A. (2012). Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0077ecst
NLM
Souza MAS de, Doria RT, Souza M de, Martino JA, Pavanello MA. Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0077ecst
Vancouver
Souza MAS de, Doria RT, Souza M de, Martino JA, Pavanello MA. Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0077ecst
Trabalho de evento
On the variability of the low-frequency noise in UTBOX SOI nMOSFETs (2012)
Simoen, Eddy ; Caño de Andrade, Maria Glória ; Almeida, Luciano Mendes; Aoulaiche, Marc; Caillat, Christian; Jurczak, Malgorzata; Claeys, Cor
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SIMOEN, Eddy et al. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0051ecst. Acesso em: 02 nov. 2024.
APA
Simoen, E., Caño de Andrade, M. G., Almeida, L. M., Aoulaiche, M., Caillat, C., Jurczak, M., & Claeys, C. (2012). On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0051ecst
NLM
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0051ecst
Vancouver
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0051ecst
Trabalho de evento
Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI (2012)
Caño de Andrade, Maria Glória ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
CAÑO DE ANDRADE, Maria Glória et al. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0111ecst. Acesso em: 02 nov. 2024.
APA
Caño de Andrade, M. G., Martino, J. A., Simoen, E., & Claeys, C. (2012). Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0111ecst
NLM
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0111ecst
Vancouver
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0111ecst
Trabalho de evento
Temperature influence on nanowire tunnel field effect transistors (2012)
Neves, Felipe Souza; Martino, Márcio Dalla Valle; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Rooyackers, Rita ; Leonelli, Daniele ; Claeys, Cor
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
NEVES, Felipe Souza et al. Temperature influence on nanowire tunnel field effect transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0223ecst. Acesso em: 02 nov. 2024.
APA
Neves, F. S., Martino, M. D. V., Agopian, P. G. D., Martino, J. A., Rooyackers, R., Leonelli, D., & Claeys, C. (2012). Temperature influence on nanowire tunnel field effect transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0223ecst
NLM
Neves FS, Martino MDV, Agopian PGD, Martino JA, Rooyackers R, Leonelli D, Claeys C. Temperature influence on nanowire tunnel field effect transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0223ecst
Vancouver
Neves FS, Martino MDV, Agopian PGD, Martino JA, Rooyackers R, Leonelli D, Claeys C. Temperature influence on nanowire tunnel field effect transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0223ecst
Trabalho de evento
Liquid helium temperature operation of graded-channel SOI nMOSFETs (2012)
Souza, Michelly de ; Kilchytska, Valeriya ; Flandre, Denis ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SOUZA, Michelly de et al. Liquid helium temperature operation of graded-channel SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0135ecst. Acesso em: 02 nov. 2024.
APA
Souza, M. de, Kilchytska, V., Flandre, D., & Pavanello, M. A. (2012). Liquid helium temperature operation of graded-channel SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0135ecst
NLM
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0135ecst
Vancouver
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0135ecst
Trabalho de evento
Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors (2012)
Trevisoli, Renan ; Doria, Rodrigo Trevisoli ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
TREVISOLI, Renan et al. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0207ecst. Acesso em: 02 nov. 2024.
APA
Trevisoli, R., Doria, R. T., Souza, M. de, & Pavanello, M. A. (2012). Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0207ecst
NLM
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0207ecst
Vancouver
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0207ecst
Trabalho de evento
Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance (2012)
Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
DORIA, Rodrigo Trevisoli et al. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0215ecst. Acesso em: 02 nov. 2024.
APA
Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0215ecst
NLM
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0215ecst
Vancouver
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0215ecst
Trabalho de evento
Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response (2012)
Roque Huanca, Danilo ; Elias, Vinícius F; Salcedo, Walter Jaimes
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
ROQUE HUANCA, Danilo e ELIAS, Vinícius F e SALCEDO, Walter Jaimes. Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0315ecst. Acesso em: 02 nov. 2024.
APA
Roque Huanca, D., Elias, V. F., & Salcedo, W. J. (2012). Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0315ecst
NLM
Roque Huanca D, Elias VF, Salcedo WJ. Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0315ecst
Vancouver
Roque Huanca D, Elias VF, Salcedo WJ. Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0315ecst
Trabalho de evento
Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS (2012)
Santos, Sara Dereste dos ; Nicoletti, Talitha; Aoulaiche, Marc; Martino, João Antonio ; Veloso, A; Jurczak, Malgorzata; Simoen, Eddy ; Claeys, Cor
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SANTOS, Sara Dereste dos et al. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf. Acesso em: 02 nov. 2024.
APA
Santos, S. D. dos, Nicoletti, T., Aoulaiche, M., Martino, J. A., Veloso, A., Jurczak, M., et al. (2012). Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. Recuperado de https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
NLM
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Vancouver
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Trabalho de evento
Simulation of PECVD SiO2 deposition using a cellular automata approach (2012)
Colombo, Fábio Belotti; Páez Carreño, Marcelo Nelson
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
COLOMBO, Fábio Belotti e PÁEZ CARREÑO, Marcelo Nelson. Simulation of PECVD SiO2 deposition using a cellular automata approach. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0297ecst. Acesso em: 02 nov. 2024.
APA
Colombo, F. B., & Páez Carreño, M. N. (2012). Simulation of PECVD SiO2 deposition using a cellular automata approach. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0297ecst
NLM
Colombo FB, Páez Carreño MN. Simulation of PECVD SiO2 deposition using a cellular automata approach [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0297ecst
Vancouver
Colombo FB, Páez Carreño MN. Simulation of PECVD SiO2 deposition using a cellular automata approach [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0297ecst
Trabalho de evento
TiO2 nanotubes production and characterization (2012)
Fraga, Tiago Marques; Albertin, Katia Franklin ; Pereyra, Inés
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
FRAGA, Tiago Marques e ALBERTIN, Katia Franklin e PEREYRA, Inés. TiO2 nanotubes production and characterization. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0199ecst. Acesso em: 02 nov. 2024.
APA
Fraga, T. M., Albertin, K. F., & Pereyra, I. (2012). TiO2 nanotubes production and characterization. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0199ecst
NLM
Fraga TM, Albertin KF, Pereyra I. TiO2 nanotubes production and characterization [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0199ecst
Vancouver
Fraga TM, Albertin KF, Pereyra I. TiO2 nanotubes production and characterization [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0199ecst
Trabalho de evento
Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes (2012)
Abe, Igor Yamamoto ; Pereyra, Inés
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
ABE, Igor Yamamoto e PEREYRA, Inés. Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0255ecst. Acesso em: 02 nov. 2024.
APA
Abe, I. Y., & Pereyra, I. (2012). Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0255ecst
NLM
Abe IY, Pereyra I. Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0255ecst
Vancouver
Abe IY, Pereyra I. Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0255ecst
Trabalho de evento
Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. (2012)
Itocazu, Vitor Tatsuo ; Sonnenberg, Victor ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
ITOCAZU, Vitor Tatsuo et al. Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0511ecst. Acesso em: 02 nov. 2024.
APA
Itocazu, V. T., Sonnenberg, V., Simoen, E., Claeys, C., & Martino, J. A. (2012). Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0511ecst
NLM
Itocazu VT, Sonnenberg V, Simoen E, Claeys C, Martino JA. Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0511ecst
Vancouver
Itocazu VT, Sonnenberg V, Simoen E, Claeys C, Martino JA. Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0511ecst
Trabalho de evento
Three-dimensional acoustic metamaterial with localized resonances (2012)
Arredondo Champi, Hipólito Alan ; Bustamante, Rina H ; Salcedo, Walter Jaimes
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
ARREDONDO CHAMPI, Hipólito Alan e BUSTAMANTE, Rina H e SALCEDO, Walter Jaimes. Three-dimensional acoustic metamaterial with localized resonances. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0543ecst. Acesso em: 02 nov. 2024.
APA
Arredondo Champi, H. A., Bustamante, R. H., & Salcedo, W. J. (2012). Three-dimensional acoustic metamaterial with localized resonances. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0543ecst
NLM
Arredondo Champi HA, Bustamante RH, Salcedo WJ. Three-dimensional acoustic metamaterial with localized resonances [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0543ecst
Vancouver
Arredondo Champi HA, Bustamante RH, Salcedo WJ. Three-dimensional acoustic metamaterial with localized resonances [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0543ecst
Trabalho de evento
Microlens array fabricated by gray-scale lithography maskless system (2012)
Cirino, Giuseppe Antonio; Lopera Aristizábal, Sergio; Montagnoli, Arlindo Neto ; Mansano, Ronaldo Domingues ; Goncalves Neto, Luiz
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidades: EP, EESC
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CIRINO, Giuseppe Antonio et al. Microlens array fabricated by gray-scale lithography maskless system. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0339ecst. Acesso em: 02 nov. 2024.
APA
Cirino, G. A., Lopera Aristizábal, S., Montagnoli, A. N., Mansano, R. D., & Goncalves Neto, L. (2012). Microlens array fabricated by gray-scale lithography maskless system. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0339ecst
NLM
Cirino GA, Lopera Aristizábal S, Montagnoli AN, Mansano RD, Goncalves Neto L. Microlens array fabricated by gray-scale lithography maskless system [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0339ecst
Vancouver
Cirino GA, Lopera Aristizábal S, Montagnoli AN, Mansano RD, Goncalves Neto L. Microlens array fabricated by gray-scale lithography maskless system [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0339ecst
Trabalho de evento
Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. (2012)
Bühler, Rudolf Theoderich ; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BÜHLER, Rudolf Theoderich et al. Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0145ecst. Acesso em: 02 nov. 2024.
APA
Bühler, R. T., Agopian, P. G. D., Simoen, E., Claeys, C., & Martino, J. A. (2012). Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0145ecst
NLM
Bühler RT, Agopian PGD, Simoen E, Claeys C, Martino JA. Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0145ecst
Vancouver
Bühler RT, Agopian PGD, Simoen E, Claeys C, Martino JA. Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0145ecst
Trabalho de evento
UTBOX SOI devices with high-k gate dielectric under analog performance (2012)
Galeti, Milene; Rodrigues, Michele; Aoulaiche, Marc; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GALETI, Milene et al. UTBOX SOI devices with high-k gate dielectric under analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0119ecst. Acesso em: 02 nov. 2024.
APA
Galeti, M., Rodrigues, M., Aoulaiche, M., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2012). UTBOX SOI devices with high-k gate dielectric under analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0119ecst
NLM
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0119ecst
Vancouver
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0119ecst
Trabalho de evento
The MOS device applied to hydrogenated gas sensor device (2012)
Magalhães, Filipe Bento ; Braga, Mauro Sergio ; Ramírez Fernandez, Francisco Javier ; Salcedo, Walter Jaimes
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MAGALHÃES, Filipe Bento et al. The MOS device applied to hydrogenated gas sensor device. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0465ecst. Acesso em: 02 nov. 2024.
APA
Magalhães, F. B., Braga, M. S., Ramírez Fernandez, F. J., & Salcedo, W. J. (2012). The MOS device applied to hydrogenated gas sensor device. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0465ecst
NLM
Magalhães FB, Braga MS, Ramírez Fernandez FJ, Salcedo WJ. The MOS device applied to hydrogenated gas sensor device [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0465ecst
Vancouver
Magalhães FB, Braga MS, Ramírez Fernandez FJ, Salcedo WJ. The MOS device applied to hydrogenated gas sensor device [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0465ecst
Trabalho de evento
Dip Pen nanolithography using a polyacrylonitrile based ink (2012)
Vega-Manzano, Omar ; Perez Medina, Gallardo J.; Furlan, Rogerio; Silva, Ana Neilde Rodrigues da ; Rosa, Luis G.
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
VEGA-MANZANO, Omar et al. Dip Pen nanolithography using a polyacrylonitrile based ink. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0241ecs. Acesso em: 02 nov. 2024.
APA
Vega-Manzano, O., Perez Medina, G. J., Furlan, R., Silva, A. N. R. da, & Rosa, L. G. (2012). Dip Pen nanolithography using a polyacrylonitrile based ink. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0241ecs
NLM
Vega-Manzano O, Perez Medina GJ, Furlan R, Silva ANR da, Rosa LG. Dip Pen nanolithography using a polyacrylonitrile based ink [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0241ecs
Vancouver
Vega-Manzano O, Perez Medina GJ, Furlan R, Silva ANR da, Rosa LG. Dip Pen nanolithography using a polyacrylonitrile based ink [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0241ecs

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