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Artigo de periodico
A FAST hardware decoder optimized for template features to obtain order book Data in low latency (2023)
Oliveira, Caio C. S ; Bonato, Vanderlei
Source: Journal of Signal Processing Systems. Unidades: ICMC, EESC
Subjects: HARDWARE, ANÁLISE DE DADOS
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OLIVEIRA, Caio C. S e BONATO, Vanderlei. A FAST hardware decoder optimized for template features to obtain order book Data in low latency. Journal of Signal Processing Systems, v. 95, p. 559-567, 2023Tradução . . Disponível em: https://doi.org/10.1007/s11265-023-01850-2. Acesso em: 17 nov. 2024.
APA
Oliveira, C. C. S., & Bonato, V. (2023). A FAST hardware decoder optimized for template features to obtain order book Data in low latency. Journal of Signal Processing Systems, 95, 559-567. doi:10.1007/s11265-023-01850-2
NLM
Oliveira CCS, Bonato V. A FAST hardware decoder optimized for template features to obtain order book Data in low latency [Internet]. Journal of Signal Processing Systems. 2023 ; 95 559-567.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1007/s11265-023-01850-2
Vancouver
Oliveira CCS, Bonato V. A FAST hardware decoder optimized for template features to obtain order book Data in low latency [Internet]. Journal of Signal Processing Systems. 2023 ; 95 559-567.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1007/s11265-023-01850-2
Trabalho de evento
Predicting Elliott Flat and Zigzag internal shapes by statistical learning on Fibonacci ratios (2023)
Santos, Rafael Ribeiro dos ; Bonato, Vanderlei ; Silva, Geraldo Nunes
Source: Proceedings. Conference titles: International Conference on Computational Science and Computational Intelligence - CSCI. Unidade: ICMC
Subjects: ANÁLISE DE SÉRIES TEMPORAIS, PREDIÇÃO, NÚMEROS DE FIBONACCI
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SANTOS, Rafael Ribeiro dos e BONATO, Vanderlei e SILVA, Geraldo Nunes. Predicting Elliott Flat and Zigzag internal shapes by statistical learning on Fibonacci ratios. 2023, Anais.. Piscataway: IEEE, 2023. Disponível em: https://doi.org/10.1109/CSCI62032.2023.00060. Acesso em: 17 nov. 2024.
APA
Santos, R. R. dos, Bonato, V., & Silva, G. N. (2023). Predicting Elliott Flat and Zigzag internal shapes by statistical learning on Fibonacci ratios. In Proceedings. Piscataway: IEEE. doi:10.1109/CSCI62032.2023.00060
NLM
Santos RR dos, Bonato V, Silva GN. Predicting Elliott Flat and Zigzag internal shapes by statistical learning on Fibonacci ratios [Internet]. Proceedings. 2023 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/CSCI62032.2023.00060
Vancouver
Santos RR dos, Bonato V, Silva GN. Predicting Elliott Flat and Zigzag internal shapes by statistical learning on Fibonacci ratios [Internet]. Proceedings. 2023 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/CSCI62032.2023.00060
Artigo de periodico
Fast resource and timing aware design optimisation for high-level synthesis (2021)
Perina, André Bannwart ; Silitonga, Arthur ; Becker, Jürgen ; Bonato, Vanderlei
Source: IEEE Transactions on Computers. Unidade: ICMC
Subjects: HARDWARE, ANÁLISE DE DESEMPENHO
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PERINA, André Bannwart et al. Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, v. 70, n. 12, p. 2070-2082, 2021Tradução . . Disponível em: https://doi.org/10.1109/TC.2021.3112260. Acesso em: 17 nov. 2024.
APA
Perina, A. B., Silitonga, A., Becker, J., & Bonato, V. (2021). Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, 70( 12), 2070-2082. doi:10.1109/TC.2021.3112260
NLM
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Vancouver
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Trabalho de evento-resumo
Lina: timing-constrained high-level synthesis performance estimator for fast DSE (2019)
Perina, André Bannwart ; Becker, Jürgen ; Bonato, Vanderlei
Source: Proceedings. Conference titles: International Conference on Field-Programmable Technology - ICFPT. Unidade: ICMC
Subjects: CIRCUITOS FPGA, BENCHMARKS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
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PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. Lina: timing-constrained high-level synthesis performance estimator for fast DSE. 2019, Anais.. Los Alamitos: IEEE, 2019. Disponível em: https://doi.org/10.1109/ICFPT47387.2019.00063. Acesso em: 17 nov. 2024.
APA
Perina, A. B., Becker, J., & Bonato, V. (2019). Lina: timing-constrained high-level synthesis performance estimator for fast DSE. In Proceedings. Los Alamitos: IEEE. doi:10.1109/ICFPT47387.2019.00063
NLM
Perina AB, Becker J, Bonato V. Lina: timing-constrained high-level synthesis performance estimator for fast DSE [Internet]. Proceedings. 2019 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/ICFPT47387.2019.00063
Vancouver
Perina AB, Becker J, Bonato V. Lina: timing-constrained high-level synthesis performance estimator for fast DSE [Internet]. Proceedings. 2019 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/ICFPT47387.2019.00063
Trabalho de evento-resumo
ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis (2019)
Perina, André Bannwart ; Becker, Jürgen ; Bonato, Vanderlei
Source: Proceedings. Conference titles: IEEE International Conference on Electronics, Circuits and Systems - ICECS. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, HARDWARE, MICROPROGRAMAÇÃO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis. 2019, Anais.. Los Alamitos: IEEE, 2019. Disponível em: https://doi.org/10.1109/ICECS46596.2019.8964669. Acesso em: 17 nov. 2024.
APA
Perina, A. B., Becker, J., & Bonato, V. (2019). ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis. In Proceedings. Los Alamitos: IEEE. doi:10.1109/ICECS46596.2019.8964669
NLM
Perina AB, Becker J, Bonato V. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis [Internet]. Proceedings. 2019 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/ICECS46596.2019.8964669
Vancouver
Perina AB, Becker J, Bonato V. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis [Internet]. Proceedings. 2019 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/ICECS46596.2019.8964669
Artigo de periodico
Scaling up modulo scheduling for high-level synthesis (2019)
Rosa, Leandro de Souza; Bouganis, Christos-Savvas; Bonato, Vanderlei
Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Unidade: ICMC
Subjects: CIRCUITOS FPGA, ALGORITMOS GENÉTICOS, COMPUTAÇÃO RECONFIGURÁVEL, ALGORITMOS DE SCHEDULING, SCHEDULING
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, Leandro de Souza e BOUGANIS, Christos-Savvas e BONATO, Vanderlei. Scaling up modulo scheduling for high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 38, n. 5, p. 912-925, 2019Tradução . . Disponível em: https://doi.org/10.1109/TCAD.2018.2834440. Acesso em: 17 nov. 2024.
APA
Rosa, L. de S., Bouganis, C. -S., & Bonato, V. (2019). Scaling up modulo scheduling for high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38( 5), 912-925. doi:10.1109/TCAD.2018.2834440
NLM
Rosa L de S, Bouganis C-S, Bonato V. Scaling up modulo scheduling for high-level synthesis [Internet]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2019 ; 38( 5): 912-925.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/TCAD.2018.2834440
Vancouver
Rosa L de S, Bouganis C-S, Bonato V. Scaling up modulo scheduling for high-level synthesis [Internet]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2019 ; 38( 5): 912-925.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/TCAD.2018.2834440
Trabalho de evento
Mapping estimator for OpenCL heterogeneous accelerators (2018)
Perina, André Bannwart ; Bonato, Vanderlei
Source: Proceedings. Conference titles: International Conference on Field-Programmable Technology - FPT. Unidade: ICMC
Subjects: APRENDIZADO COMPUTACIONAL, EFICIÊNCIA ENERGÉTICA, ESTATÍSTICA COMPUTACIONAL
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart e BONATO, Vanderlei. Mapping estimator for OpenCL heterogeneous accelerators. 2018, Anais.. Piscataway: IEEE, 2018. Disponível em: https://doi.org/10.1109/FPT.2018.00057. Acesso em: 17 nov. 2024.
APA
Perina, A. B., & Bonato, V. (2018). Mapping estimator for OpenCL heterogeneous accelerators. In Proceedings. Piscataway: IEEE. doi:10.1109/FPT.2018.00057
NLM
Perina AB, Bonato V. Mapping estimator for OpenCL heterogeneous accelerators [Internet]. Proceedings. 2018 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/FPT.2018.00057
Vancouver
Perina AB, Bonato V. Mapping estimator for OpenCL heterogeneous accelerators [Internet]. Proceedings. 2018 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/FPT.2018.00057
Trabalho de evento
Scaling up loop pipelining for high-level synthesis: a non-iterative approach (2018)
Rosa, Leandro de Souza ; Bonato, Vanderlei ; Bouganis, Christos-Savvas
Source: Proceedings. Conference titles: International Conference on Field-Programmable Technology - FPT. Unidade: ICMC
Subjects: HARDWARE, ANÁLISE DE DESEMPENHO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, Leandro de Souza e BONATO, Vanderlei e BOUGANIS, Christos-Savvas. Scaling up loop pipelining for high-level synthesis: a non-iterative approach. 2018, Anais.. Piscataway: IEEE, 2018. Disponível em: https://doi.org/10.1109/FPT.2018.00020. Acesso em: 17 nov. 2024.
APA
Rosa, L. de S., Bonato, V., & Bouganis, C. -S. (2018). Scaling up loop pipelining for high-level synthesis: a non-iterative approach. In Proceedings. Piscataway: IEEE. doi:10.1109/FPT.2018.00020
NLM
Rosa L de S, Bonato V, Bouganis C-S. Scaling up loop pipelining for high-level synthesis: a non-iterative approach [Internet]. Proceedings. 2018 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/FPT.2018.00020
Vancouver
Rosa L de S, Bonato V, Bouganis C-S. Scaling up loop pipelining for high-level synthesis: a non-iterative approach [Internet]. Proceedings. 2018 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/FPT.2018.00020
Trabalho de evento-resumo
Exploiting Kant and Kimura’s matrix inversion algorithm on FPGA (2017)
Perina, André Bannwart; Matias, Paulo; Lima, João Miguel Gago Pontes de Brito; Marques, Eduardo ; Bonato, Vanderlei
Source: Proceedings. Conference titles: Euromicro Conference on Digital System Design - DSD. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart et al. Exploiting Kant and Kimura’s matrix inversion algorithm on FPGA. 2017, Anais.. Los Alamitos, CA: IEEE, 2017. Disponível em: https://doi.org/10.1109/DSD.2017.32. Acesso em: 17 nov. 2024.
APA
Perina, A. B., Matias, P., Lima, J. M. G. P. de B., Marques, E., & Bonato, V. (2017). Exploiting Kant and Kimura’s matrix inversion algorithm on FPGA. In Proceedings. Los Alamitos, CA: IEEE. doi:10.1109/DSD.2017.32
NLM
Perina AB, Matias P, Lima JMGP de B, Marques E, Bonato V. Exploiting Kant and Kimura’s matrix inversion algorithm on FPGA [Internet]. Proceedings. 2017 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/DSD.2017.32
Vancouver
Perina AB, Matias P, Lima JMGP de B, Marques E, Bonato V. Exploiting Kant and Kimura’s matrix inversion algorithm on FPGA [Internet]. Proceedings. 2017 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/DSD.2017.32
Artigo de periodico
Application-oriented cache memory configuration for energy efficiency in multi-cores (2015)
Silva, Bruno de Abreu; Cuminato, Lucas A; Delbem, Alexandre Cláudio Botazzo ; Diniz, Pedro C; Bonato, Vanderlei
Source: IET Computers and Digital Techniques. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
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ABNT
SILVA, Bruno de Abreu et al. Application-oriented cache memory configuration for energy efficiency in multi-cores. IET Computers and Digital Techniques, v. Fe 2015, n. 1, p. 73-81, 2015Tradução . . Disponível em: https://doi.org/10.1049/iet-cdt.2014.0091. Acesso em: 17 nov. 2024.
APA
Silva, B. de A., Cuminato, L. A., Delbem, A. C. B., Diniz, P. C., & Bonato, V. (2015). Application-oriented cache memory configuration for energy efficiency in multi-cores. IET Computers and Digital Techniques, Fe 2015( 1), 73-81. doi:10.1049/iet-cdt.2014.0091
NLM
Silva B de A, Cuminato LA, Delbem ACB, Diniz PC, Bonato V. Application-oriented cache memory configuration for energy efficiency in multi-cores [Internet]. IET Computers and Digital Techniques. 2015 ; Fe 2015( 1): 73-81.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1049/iet-cdt.2014.0091
Vancouver
Silva B de A, Cuminato LA, Delbem ACB, Diniz PC, Bonato V. Application-oriented cache memory configuration for energy efficiency in multi-cores [Internet]. IET Computers and Digital Techniques. 2015 ; Fe 2015( 1): 73-81.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1049/iet-cdt.2014.0091
Trabalho de evento
Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems (2015)
Silva, Bruno; Delbem, Alexandre Cláudio Botazzo ; Bonato, Vanderlei ; Diniz, Pedro C
Source: Proceedings. Conference titles: International Conference on ReConFigurable Computing and FPGAs - ReConFig 2015. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Bruno et al. Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems. 2015, Anais.. Piscataway, NJ: IEEE, 2015. Disponível em: https://doi.org/10.1109/ReConFig.2015.7393355. Acesso em: 17 nov. 2024.
APA
Silva, B., Delbem, A. C. B., Bonato, V., & Diniz, P. C. (2015). Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems. In Proceedings. Piscataway, NJ: IEEE. doi:10.1109/ReConFig.2015.7393355
NLM
Silva B, Delbem ACB, Bonato V, Diniz PC. Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems [Internet]. Proceedings. 2015 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/ReConFig.2015.7393355
Vancouver
Silva B, Delbem ACB, Bonato V, Diniz PC. Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems [Internet]. Proceedings. 2015 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/ReConFig.2015.7393355
Trabalho de evento-resumo
Parameterizable ethernet network-on-chip architecture on FPGA (2015)
Cunha Junior, Helio Fernandes da; Silva, Bruno de Abreu; Bonato, Vanderlei
Source: Proceedings. Conference titles: Euromicro Conference on Digital System Design - DSD. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
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ABNT
CUNHA JUNIOR, Helio Fernandes da e SILVA, Bruno de Abreu e BONATO, Vanderlei. Parameterizable ethernet network-on-chip architecture on FPGA. 2015, Anais.. Los Alamitos, CA: IEEE, 2015. Disponível em: https://doi.org/10.1109/DSD.2015.101. Acesso em: 17 nov. 2024.
APA
Cunha Junior, H. F. da, Silva, B. de A., & Bonato, V. (2015). Parameterizable ethernet network-on-chip architecture on FPGA. In Proceedings. Los Alamitos, CA: IEEE. doi:10.1109/DSD.2015.101
NLM
Cunha Junior HF da, Silva B de A, Bonato V. Parameterizable ethernet network-on-chip architecture on FPGA [Internet]. Proceedings. 2015 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/DSD.2015.101
Vancouver
Cunha Junior HF da, Silva B de A, Bonato V. Parameterizable ethernet network-on-chip architecture on FPGA [Internet]. Proceedings. 2015 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/DSD.2015.101
Trabalho de evento
Run-time cache configuration for the LEON-3 embedded processor (2015)
Silva, Bruno A; Cuminato, Lucas A; Bonato, Vanderlei ; Diniz, Pedro C
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design - SBCCI. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Bruno A et al. Run-time cache configuration for the LEON-3 embedded processor. 2015, Anais.. New York: ACM, 2015. Disponível em: https://doi.org/10.1145/2800986.2801026. Acesso em: 17 nov. 2024.
APA
Silva, B. A., Cuminato, L. A., Bonato, V., & Diniz, P. C. (2015). Run-time cache configuration for the LEON-3 embedded processor. In Proceedings. New York: ACM. doi:10.1145/2800986.2801026
NLM
Silva BA, Cuminato LA, Bonato V, Diniz PC. Run-time cache configuration for the LEON-3 embedded processor [Internet]. Proceedings. 2015 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1145/2800986.2801026
Vancouver
Silva BA, Cuminato LA, Bonato V, Diniz PC. Run-time cache configuration for the LEON-3 embedded processor [Internet]. Proceedings. 2015 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1145/2800986.2801026
Artigo de periodico
Practical education fostered by research projects in an embedded systems course (2014)
Bonato, Vanderlei ; Fernandes, Marcio Merino; Cardoso, João M. P; Marques, Eduardo
Source: International Journal of Reconfigurable Computing. Unidade: ICMC
Subjects: ARQUITETURA E ORGANIZAÇÃO DE COMPUTADORES, SISTEMAS EMBUTIDOS, ROBÓTICA, COMPUTAÇÃO EVOLUTIVA
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ABNT
BONATO, Vanderlei et al. Practical education fostered by research projects in an embedded systems course. International Journal of Reconfigurable Computing, v. 2014, p. 1-12, 2014Tradução . . Disponível em: https://doi.org/10.1155/2014/287205. Acesso em: 17 nov. 2024.
APA
Bonato, V., Fernandes, M. M., Cardoso, J. M. P., & Marques, E. (2014). Practical education fostered by research projects in an embedded systems course. International Journal of Reconfigurable Computing, 2014, 1-12. doi:10.1155/2014/287205
NLM
Bonato V, Fernandes MM, Cardoso JMP, Marques E. Practical education fostered by research projects in an embedded systems course [Internet]. International Journal of Reconfigurable Computing. 2014 ; 2014 1-12.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1155/2014/287205
Vancouver
Bonato V, Fernandes MM, Cardoso JMP, Marques E. Practical education fostered by research projects in an embedded systems course [Internet]. International Journal of Reconfigurable Computing. 2014 ; 2014 1-12.[citado 2024 nov. 17 ] Available from: https://doi.org/10.1155/2014/287205
Artigo de periodico
A parallel hardware architecture based on node-depth encoding to solve network design problems (2014)
Gois, Marcilyanne M.; Matias, Paulo; Perina, André B; Bonato, Vanderlei ; Delbem, Alexandre Cláudio Botazzo
Source: International Journal of Natural Computing Research. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GOIS, Marcilyanne M. et al. A parallel hardware architecture based on node-depth encoding to solve network design problems. International Journal of Natural Computing Research, v. 4, n. Ja-Mar. 2014, p. 54-75, 2014Tradução . . Acesso em: 17 nov. 2024.
APA
Gois, M. M., Matias, P., Perina, A. B., Bonato, V., & Delbem, A. C. B. (2014). A parallel hardware architecture based on node-depth encoding to solve network design problems. International Journal of Natural Computing Research, 4( Ja-Mar. 2014), 54-75.
NLM
Gois MM, Matias P, Perina AB, Bonato V, Delbem ACB. A parallel hardware architecture based on node-depth encoding to solve network design problems. International Journal of Natural Computing Research. 2014 ; 4( Ja-Mar. 2014): 54-75.[citado 2024 nov. 17 ]
Vancouver
Gois MM, Matias P, Perina AB, Bonato V, Delbem ACB. A parallel hardware architecture based on node-depth encoding to solve network design problems. International Journal of Natural Computing Research. 2014 ; 4( Ja-Mar. 2014): 54-75.[citado 2024 nov. 17 ]
Trabalho de evento
Designing embedded systems with MARTE: a PIM to PSM converter (2012)
Medeiros, Roberto de; Gois, Marcilyanne M.; Rossi, Drausio L.; Bonato, Vanderlei
Source: Proceedings. Conference titles: International Symposium on Industrial Embedded Systems - SIES 2012. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, ROBÓTICA, COMPUTAÇÃO EVOLUTIVA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MEDEIROS, Roberto de et al. Designing embedded systems with MARTE: a PIM to PSM converter. 2012, Anais.. Piscataway, NJ: IEEE Industrial Electronics Society, 2012. . Acesso em: 17 nov. 2024.
APA
Medeiros, R. de, Gois, M. M., Rossi, D. L., & Bonato, V. (2012). Designing embedded systems with MARTE: a PIM to PSM converter. In Proceedings. Piscataway, NJ: IEEE Industrial Electronics Society.
NLM
Medeiros R de, Gois MM, Rossi DL, Bonato V. Designing embedded systems with MARTE: a PIM to PSM converter. Proceedings. 2012 ;[citado 2024 nov. 17 ]
Vancouver
Medeiros R de, Gois MM, Rossi DL, Bonato V. Designing embedded systems with MARTE: a PIM to PSM converter. Proceedings. 2012 ;[citado 2024 nov. 17 ]
Trabalho de evento
A tool to support Bluespec SystemVerilog coding based on UML diagrams (2012)
Durand, Sérgio H. M.; Bonato, Vanderlei
Source: Proceedings. Conference titles: Annual Conference of the IEEE Industrial Electronics Society - IECON 2012. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
DURAND, Sérgio H. M. e BONATO, Vanderlei. A tool to support Bluespec SystemVerilog coding based on UML diagrams. 2012, Anais.. New York: IEEE, 2012. . Acesso em: 17 nov. 2024.
APA
Durand, S. H. M., & Bonato, V. (2012). A tool to support Bluespec SystemVerilog coding based on UML diagrams. In Proceedings. New York: IEEE.
NLM
Durand SHM, Bonato V. A tool to support Bluespec SystemVerilog coding based on UML diagrams. Proceedings. 2012 ;[citado 2024 nov. 17 ]
Vancouver
Durand SHM, Bonato V. A tool to support Bluespec SystemVerilog coding based on UML diagrams. Proceedings. 2012 ;[citado 2024 nov. 17 ]
Trabalho de evento-resumo
Power/performance optimization in FPGA-based asymmetric multi-core systems (2012)
Silva, Bruno de Abreu; Bonato, Vanderlei
Source: Proceedings. Conference titles: International Conference on Field Programmable Logic and Applications - FPL 2012. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Bruno de Abreu e BONATO, Vanderlei. Power/performance optimization in FPGA-based asymmetric multi-core systems. 2012, Anais.. New York: IEEE, 2012. Disponível em: https://doi.org/10.1109/FPL.2012.6339197. Acesso em: 17 nov. 2024.
APA
Silva, B. de A., & Bonato, V. (2012). Power/performance optimization in FPGA-based asymmetric multi-core systems. In Proceedings. New York: IEEE. doi:10.1109/FPL.2012.6339197
NLM
Silva B de A, Bonato V. Power/performance optimization in FPGA-based asymmetric multi-core systems [Internet]. Proceedings. 2012 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/FPL.2012.6339197
Vancouver
Silva B de A, Bonato V. Power/performance optimization in FPGA-based asymmetric multi-core systems [Internet]. Proceedings. 2012 ;[citado 2024 nov. 17 ] Available from: https://doi.org/10.1109/FPL.2012.6339197
Trabalho de evento
Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors (2012)
Silva, Bruno de Abreu; Cuminato, Lucas Albers; Bonato, Vanderlei
Source: Proceedings. Conference titles: International Conference on Reconfigurable Computing and FPGAs - ReConFig 2012. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Bruno de Abreu e CUMINATO, Lucas Albers e BONATO, Vanderlei. Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. 2012, Anais.. New York: IEEE, 2012. . Acesso em: 17 nov. 2024.
APA
Silva, B. de A., Cuminato, L. A., & Bonato, V. (2012). Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. In Proceedings. New York: IEEE.
NLM
Silva B de A, Cuminato LA, Bonato V. Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. Proceedings. 2012 ;[citado 2024 nov. 17 ]
Vancouver
Silva B de A, Cuminato LA, Bonato V. Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. Proceedings. 2012 ;[citado 2024 nov. 17 ]
Trabalho de evento
Designing FPGA-based embedded systems with MARTE: a PIM to PSM converter (2012)
Durand, Sérgio H. M.; Gois, Marcilyanne M.; Bonato, Vanderlei
Source: Proceedings. Conference titles: Annual Conference of the IEEE Industrial Electronics Society - IECON 2012. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
DURAND, Sérgio H. M. e GOIS, Marcilyanne M. e BONATO, Vanderlei. Designing FPGA-based embedded systems with MARTE: a PIM to PSM converter. 2012, Anais.. New York: IEEE, 2012. . Acesso em: 17 nov. 2024.
APA
Durand, S. H. M., Gois, M. M., & Bonato, V. (2012). Designing FPGA-based embedded systems with MARTE: a PIM to PSM converter. In Proceedings. New York: IEEE.
NLM
Durand SHM, Gois MM, Bonato V. Designing FPGA-based embedded systems with MARTE: a PIM to PSM converter. Proceedings. 2012 ;[citado 2024 nov. 17 ]
Vancouver
Durand SHM, Gois MM, Bonato V. Designing FPGA-based embedded systems with MARTE: a PIM to PSM converter. Proceedings. 2012 ;[citado 2024 nov. 17 ]

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