Scaling up loop pipelining for high-level synthesis: a non-iterative approach (2018)
- Authors:
- USP affiliated authors: BONATO, VANDERLEI - ICMC ; ROSA, LEANDRO DE SOUZA - ICMC
- Unidade: ICMC
- DOI: 10.1109/FPT.2018.00020
- Subjects: HARDWARE; ANÁLISE DE DESEMPENHO
- Agências de fomento:
- Language: Inglês
- Imprenta:
- Publisher: IEEE
- Publisher place: Piscataway
- Date published: 2018
- Source:
- Título: Proceedings
- Conference titles: International Conference on Field-Programmable Technology - FPT
- Status:
- Nenhuma versão em acesso aberto identificada
-
ABNT
ROSA, Leandro de Souza e BONATO, Vanderlei e BOUGANIS, Christos-Savvas. Scaling up loop pipelining for high-level synthesis: a non-iterative approach. 2018, Anais.. Piscataway: IEEE, 2018. Disponível em: https://doi.org/10.1109/FPT.2018.00020. Acesso em: 10 abr. 2026. -
APA
Rosa, L. de S., Bonato, V., & Bouganis, C. -S. (2018). Scaling up loop pipelining for high-level synthesis: a non-iterative approach. In Proceedings. Piscataway: IEEE. doi:10.1109/FPT.2018.00020 -
NLM
Rosa L de S, Bonato V, Bouganis C-S. Scaling up loop pipelining for high-level synthesis: a non-iterative approach [Internet]. Proceedings. 2018 ;[citado 2026 abr. 10 ] Available from: https://doi.org/10.1109/FPT.2018.00020 -
Vancouver
Rosa L de S, Bonato V, Bouganis C-S. Scaling up loop pipelining for high-level synthesis: a non-iterative approach [Internet]. Proceedings. 2018 ;[citado 2026 abr. 10 ] Available from: https://doi.org/10.1109/FPT.2018.00020 - Fast Code Exploration for Pipeline Processing in FPGA Accelerators
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