Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors (2012)
- Authors:
- Autor USP: BONATO, VANDERLEI - ICMC
- Unidade: ICMC
- Subjects: SISTEMAS EMBUTIDOS; COMPUTAÇÃO EVOLUTIVA; ROBÓTICA
- Language: Inglês
- Imprenta:
- ISBN: 9781467329217
- Source:
- Título: Proceedings
- Conference titles: International Conference on Reconfigurable Computing and FPGAs - ReConFig 2012
-
ABNT
SILVA, Bruno de Abreu e CUMINATO, Lucas Albers e BONATO, Vanderlei. Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. 2012, Anais.. New York: IEEE, 2012. . Acesso em: 27 dez. 2025. -
APA
Silva, B. de A., Cuminato, L. A., & Bonato, V. (2012). Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. In Proceedings. New York: IEEE. -
NLM
Silva B de A, Cuminato LA, Bonato V. Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. Proceedings. 2012 ;[citado 2025 dez. 27 ] -
Vancouver
Silva B de A, Cuminato LA, Bonato V. Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. Proceedings. 2012 ;[citado 2025 dez. 27 ] - A tool to support Bluespec SystemVerilog coding based on UML diagrams
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