Application-oriented cache memory configuration for energy efficiency in multi-cores (2015)
- Authors:
- USP affiliated authors: DELBEM, ALEXANDRE CLÁUDIO BOTAZZO - ICMC ; BONATO, VANDERLEI - ICMC
- Unidade: ICMC
- DOI: 10.1049/iet-cdt.2014.0091
- Subjects: SISTEMAS EMBUTIDOS; COMPUTAÇÃO EVOLUTIVA; ROBÓTICA
- Language: Português
- Imprenta:
- Publisher place: Piscataway, NJ
- Date published: 2015
- Source:
- Título: IET Computers and Digital Techniques
- ISSN: 1751-8601
- Volume/Número/Paginação/Ano: v. 9, n. 1, p. 73-81, Fev. 2015
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
SILVA, Bruno de Abreu et al. Application-oriented cache memory configuration for energy efficiency in multi-cores. IET Computers and Digital Techniques, v. Fe 2015, n. 1, p. 73-81, 2015Tradução . . Disponível em: https://doi.org/10.1049/iet-cdt.2014.0091. Acesso em: 12 fev. 2026. -
APA
Silva, B. de A., Cuminato, L. A., Delbem, A. C. B., Diniz, P. C., & Bonato, V. (2015). Application-oriented cache memory configuration for energy efficiency in multi-cores. IET Computers and Digital Techniques, Fe 2015( 1), 73-81. doi:10.1049/iet-cdt.2014.0091 -
NLM
Silva B de A, Cuminato LA, Delbem ACB, Diniz PC, Bonato V. Application-oriented cache memory configuration for energy efficiency in multi-cores [Internet]. IET Computers and Digital Techniques. 2015 ; Fe 2015( 1): 73-81.[citado 2026 fev. 12 ] Available from: https://doi.org/10.1049/iet-cdt.2014.0091 -
Vancouver
Silva B de A, Cuminato LA, Delbem ACB, Diniz PC, Bonato V. Application-oriented cache memory configuration for energy efficiency in multi-cores [Internet]. IET Computers and Digital Techniques. 2015 ; Fe 2015( 1): 73-81.[citado 2026 fev. 12 ] Available from: https://doi.org/10.1049/iet-cdt.2014.0091 - A parallel hardware architecture based on node-depth encoding to solve network design problems
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- Special issue on applied reconfigurable computing [Editorial]
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Informações sobre o DOI: 10.1049/iet-cdt.2014.0091 (Fonte: oaDOI API)
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