ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis (2019)
- Authors:
- USP affiliated authors: BONATO, VANDERLEI - ICMC ; PERINA, ANDRE BANNWART - ICMC
- Unidade: ICMC
- DOI: 10.1109/ICECS46596.2019.8964669
- Subjects: COMPUTAÇÃO RECONFIGURÁVEL; HARDWARE; MICROPROGRAMAÇÃO
- Agências de fomento:
- Language: Inglês
- Imprenta:
- Publisher: IEEE
- Publisher place: Los Alamitos
- Date published: 2019
- Source:
- Título: Proceedings
- Conference titles: IEEE International Conference on Electronics, Circuits and Systems - ICECS
- Status:
- Nenhuma versão em acesso aberto identificada
-
ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis. 2019, Anais.. Los Alamitos: IEEE, 2019. Disponível em: https://doi.org/10.1109/ICECS46596.2019.8964669. Acesso em: 08 abr. 2026. -
APA
Perina, A. B., Becker, J., & Bonato, V. (2019). ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis. In Proceedings. Los Alamitos: IEEE. doi:10.1109/ICECS46596.2019.8964669 -
NLM
Perina AB, Becker J, Bonato V. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis [Internet]. Proceedings. 2019 ;[citado 2026 abr. 08 ] Available from: https://doi.org/10.1109/ICECS46596.2019.8964669 -
Vancouver
Perina AB, Becker J, Bonato V. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis [Internet]. Proceedings. 2019 ;[citado 2026 abr. 08 ] Available from: https://doi.org/10.1109/ICECS46596.2019.8964669 - Memory aware design optimisation for high-level synthesis
- Mapping estimator for OpenCL heterogeneous accelerators
- Lina: timing-constrained high-level synthesis performance estimator for fast DSE
- Fast resource and timing aware design optimisation for high-level synthesis
- Lina: a fast design optimisation tool for software-based FPGA programming
- Designing FPGA-based embedded systems with MARTE: a PIM to PSM converter
- LALPC: exploiting parallelism from FPGAS using C language
- Run-time cache configuration for the LEON-3 embedded processor
- Special issue on applied reconfigurable computing [Editorial]
- Scaling up modulo scheduling for high-level synthesis
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