Memory aware design optimisation for high-level synthesis (2024)
- Authors:
- USP affiliated authors: BONATO, VANDERLEI - ICMC ; PERINA, ANDRE BANNWART - ICMC
- Unidade: ICMC
- DOI: 10.1007/s11265-024-01938-3
- Subjects: COMPUTAÇÃO RECONFIGURÁVEL; CIRCUITOS FPGA; ARQUITETURA DE SOFTWARE
- Keywords: Reconfigurable computing; High-level synthesis; Design space optimisation; Model-based estimation
- Agências de fomento:
- Language: Inglês
- Imprenta:
- Source:
- Título: Journal of Signal Processing Systems
- ISSN: 1939-8018
- Volume/Número/Paginação/Ano: v. 96, n. 11, p. 651-671, Nov. 2024
- Status:
- Nenhuma versão em acesso aberto identificada
-
ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. Memory aware design optimisation for high-level synthesis. Journal of Signal Processing Systems, v. No 2024, n. 11, p. 651-671, 2024Tradução . . Disponível em: https://doi.org/10.1007/s11265-024-01938-3. Acesso em: 08 abr. 2026. -
APA
Perina, A. B., Becker, J., & Bonato, V. (2024). Memory aware design optimisation for high-level synthesis. Journal of Signal Processing Systems, No 2024( 11), 651-671. doi:10.1007/s11265-024-01938-3 -
NLM
Perina AB, Becker J, Bonato V. Memory aware design optimisation for high-level synthesis [Internet]. Journal of Signal Processing Systems. 2024 ; No 2024( 11): 651-671.[citado 2026 abr. 08 ] Available from: https://doi.org/10.1007/s11265-024-01938-3 -
Vancouver
Perina AB, Becker J, Bonato V. Memory aware design optimisation for high-level synthesis [Internet]. Journal of Signal Processing Systems. 2024 ; No 2024( 11): 651-671.[citado 2026 abr. 08 ] Available from: https://doi.org/10.1007/s11265-024-01938-3 - Mapping estimator for OpenCL heterogeneous accelerators
- ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis
- Lina: timing-constrained high-level synthesis performance estimator for fast DSE
- Fast resource and timing aware design optimisation for high-level synthesis
- Lina: a fast design optimisation tool for software-based FPGA programming
- Designing FPGA-based embedded systems with MARTE: a PIM to PSM converter
- LALPC: exploiting parallelism from FPGAS using C language
- Run-time cache configuration for the LEON-3 embedded processor
- Special issue on applied reconfigurable computing [Editorial]
- Scaling up modulo scheduling for high-level synthesis
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