ReP USP - Resultado da busca

Trabalho de evento
Analog performance of dynamic threshold voltage SOI MOSFET (2008)
Amaro, Jefferson Oliveira; Agopian, Paula Ghedini Der ; Martino, João Antonio
Fonte: SBMICRO 2008: Anais. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
AMARO, Jefferson Oliveira e AGOPIAN, Paula Ghedini Der e MARTINO, João Antonio. Analog performance of dynamic threshold voltage SOI MOSFET. 2008, Anais.. Pennington: The Electrochemical Society, 2008. . Acesso em: 15 nov. 2025.
APA
Amaro, J. O., Agopian, P. G. D., & Martino, J. A. (2008). Analog performance of dynamic threshold voltage SOI MOSFET. In SBMICRO 2008: Anais. Pennington: The Electrochemical Society.
NLM
Amaro JO, Agopian PGD, Martino JA. Analog performance of dynamic threshold voltage SOI MOSFET. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Vancouver
Amaro JO, Agopian PGD, Martino JA. Analog performance of dynamic threshold voltage SOI MOSFET. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Trabalho de evento
Halo optimization for 0.13 micron SOI CMOS technology (2008)
Agopian, Paula Ghedini Der ; Arrabaça, Julia Maria; Martino, João Antonio
Fonte: SBMICRO 2008: Anais. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
AGOPIAN, Paula Ghedini Der e ARRABAÇA, Julia Maria e MARTINO, João Antonio. Halo optimization for 0.13 micron SOI CMOS technology. 2008, Anais.. Pennington: The Electrochemical Society, 2008. . Acesso em: 15 nov. 2025.
APA
Agopian, P. G. D., Arrabaça, J. M., & Martino, J. A. (2008). Halo optimization for 0.13 micron SOI CMOS technology. In SBMICRO 2008: Anais. Pennington: The Electrochemical Society.
NLM
Agopian PGD, Arrabaça JM, Martino JA. Halo optimization for 0.13 micron SOI CMOS technology. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Vancouver
Agopian PGD, Arrabaça JM, Martino JA. Halo optimization for 0.13 micron SOI CMOS technology. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Trabalho de evento
Corner effect on capacitance-voltage curves in triple gate FinFET (2008)
Rodrigues, Michele; Sonnenberg, Victor ; Martino, João Antonio
Fonte: SBMICRO 2008: Anais. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
RODRIGUES, Michele e SONNENBERG, Victor e MARTINO, João Antonio. Corner effect on capacitance-voltage curves in triple gate FinFET. 2008, Anais.. Pennington: The Electrochemical Society, 2008. . Acesso em: 15 nov. 2025.
APA
Rodrigues, M., Sonnenberg, V., & Martino, J. A. (2008). Corner effect on capacitance-voltage curves in triple gate FinFET. In SBMICRO 2008: Anais. Pennington: The Electrochemical Society.
NLM
Rodrigues M, Sonnenberg V, Martino JA. Corner effect on capacitance-voltage curves in triple gate FinFET. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Vancouver
Rodrigues M, Sonnenberg V, Martino JA. Corner effect on capacitance-voltage curves in triple gate FinFET. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Trabalho de evento
Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs (2008)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Rooyackers, Rita; Collaert, Nadine ; Claeys, Cor
Fonte: SBMICRO 2008: Anais. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
PAVANELLO, Marcelo Antonio et al. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. 2008, Anais.. Pennington: The Electrochemical Society, 2008. . Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., Rooyackers, R., Collaert, N., & Claeys, C. (2008). Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. In SBMICRO 2008: Anais. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Vancouver
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Trabalho de evento
Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point (2008)
Camillo, Luciano Mendes; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: SBMICRO 2008: Anais. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
CAMILLO, Luciano Mendes et al. Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point. 2008, Anais.. Pennington: The Electrochemical Society, 2008. . Acesso em: 15 nov. 2025.
APA
Camillo, L. M., Martino, J. A., Simoen, E., & Claeys, C. (2008). Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point. In SBMICRO 2008: Anais. Pennington: The Electrochemical Society.
NLM
Camillo LM, Martino JA, Simoen E, Claeys C. Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Vancouver
Camillo LM, Martino JA, Simoen E, Claeys C. Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point. SBMICRO 2008: Anais. 2008 ;[citado 2025 nov. 15 ]
Trabalho de evento
Low temperature operation of undoped body triple-gate finFETs from an analog perspective (2007)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Rooyackers, Rita; Collaert, Nadine ; Claeys, Cor
Fonte: SBMicro 2007. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
PAVANELLO, Marcelo Antonio et al. Low temperature operation of undoped body triple-gate finFETs from an analog perspective. 2007, Anais.. Pennington: The Electrochemical Society, 2007. . Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., Rooyackers, R., Collaert, N., & Claeys, C. (2007). Low temperature operation of undoped body triple-gate finFETs from an analog perspective. In SBMicro 2007. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Low temperature operation of undoped body triple-gate finFETs from an analog perspective. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Vancouver
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Low temperature operation of undoped body triple-gate finFETs from an analog perspective. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Trabalho de evento
The impact of the gate oxide thickness reduction on the gate induced floating body effect in SOI nMOSFETs (2007)
Agopian, Paula Ghedini Der ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: SBMicro 2007. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assuntos: MICROELETRÔNICA, CIRCUITOS INTEGRADOS MOS
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ABNT
AGOPIAN, Paula Ghedini Der et al. The impact of the gate oxide thickness reduction on the gate induced floating body effect in SOI nMOSFETs. 2007, Anais.. Pennington: The Electrochemical Society, 2007. . Acesso em: 15 nov. 2025.
APA
Agopian, P. G. D., Martino, J. A., Simoen, E., & Claeys, C. (2007). The impact of the gate oxide thickness reduction on the gate induced floating body effect in SOI nMOSFETs. In SBMicro 2007. Pennington: The Electrochemical Society.
NLM
Agopian PGD, Martino JA, Simoen E, Claeys C. The impact of the gate oxide thickness reduction on the gate induced floating body effect in SOI nMOSFETs. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Vancouver
Agopian PGD, Martino JA, Simoen E, Claeys C. The impact of the gate oxide thickness reduction on the gate induced floating body effect in SOI nMOSFETs. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Trabalho de evento
Influence of the N-type finFET width on the zero temperature coefficient (2007)
Bellodi, Marcello; Martino, João Antonio ; Claeys, Cor ; Camillo, Luciano Mendes; Simoen, Eddy
Fonte: SBMicro 2007. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
BELLODI, Marcello et al. Influence of the N-type finFET width on the zero temperature coefficient. 2007, Anais.. Pennington: The Electrochemical Society, 2007. . Acesso em: 15 nov. 2025.
APA
Bellodi, M., Martino, J. A., Claeys, C., Camillo, L. M., & Simoen, E. (2007). Influence of the N-type finFET width on the zero temperature coefficient. In SBMicro 2007. Pennington: The Electrochemical Society.
NLM
Bellodi M, Martino JA, Claeys C, Camillo LM, Simoen E. Influence of the N-type finFET width on the zero temperature coefficient. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Vancouver
Bellodi M, Martino JA, Claeys C, Camillo LM, Simoen E. Influence of the N-type finFET width on the zero temperature coefficient. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Trabalho de evento
Triple gate finFET parameter extraction using high frequency capacitance - voltage curves (2007)
Rodrigues, Michele; Sonnenberg, Victor ; Martino, João Antonio
Fonte: SBMicro 2007. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
RODRIGUES, Michele e SONNENBERG, Victor e MARTINO, João Antonio. Triple gate finFET parameter extraction using high frequency capacitance - voltage curves. 2007, Anais.. Pennington: The Electrochemical Society, 2007. . Acesso em: 15 nov. 2025.
APA
Rodrigues, M., Sonnenberg, V., & Martino, J. A. (2007). Triple gate finFET parameter extraction using high frequency capacitance - voltage curves. In SBMicro 2007. Pennington: The Electrochemical Society.
NLM
Rodrigues M, Sonnenberg V, Martino JA. Triple gate finFET parameter extraction using high frequency capacitance - voltage curves. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Vancouver
Rodrigues M, Sonnenberg V, Martino JA. Triple gate finFET parameter extraction using high frequency capacitance - voltage curves. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Trabalho de evento
Physical characterization and reliability aspects of MuGFETs (2007)
Claeys, Cor ; Simoen, Eddy ; Rafi, J.M.; Pavanello, Marcelo Antonio ; Martino, João Antonio
Fonte: SBMicro 2007. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
CLAEYS, Cor et al. Physical characterization and reliability aspects of MuGFETs. 2007, Anais.. Pennington: The Electrochemical Society, 2007. . Acesso em: 15 nov. 2025.
APA
Claeys, C., Simoen, E., Rafi, J. M., Pavanello, M. A., & Martino, J. A. (2007). Physical characterization and reliability aspects of MuGFETs. In SBMicro 2007. Pennington: The Electrochemical Society.
NLM
Claeys C, Simoen E, Rafi JM, Pavanello MA, Martino JA. Physical characterization and reliability aspects of MuGFETs. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Vancouver
Claeys C, Simoen E, Rafi JM, Pavanello MA, Martino JA. Physical characterization and reliability aspects of MuGFETs. SBMicro 2007. 2007 ;[citado 2025 nov. 15 ]
Trabalho de evento
Analysis of the linear kink effect in partially depleted SOI nMOSFETs (2005)
Agopian, Paula Ghedini Der ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: Microelectronics Technology and Devices SBMICRO 2005. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
AGOPIAN, Paula Ghedini Der et al. Analysis of the linear kink effect in partially depleted SOI nMOSFETs. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 15 nov. 2025.
APA
Agopian, P. G. D., Martino, J. A., Simoen, E., & Claeys, C. (2005). Analysis of the linear kink effect in partially depleted SOI nMOSFETs. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Agopian PGD, Martino JA, Simoen E, Claeys C. Analysis of the linear kink effect in partially depleted SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Vancouver
Agopian PGD, Martino JA, Simoen E, Claeys C. Analysis of the linear kink effect in partially depleted SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Trabalho de evento
Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K (2005)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: Microelectronics Technology and Devices SBMICRO 2005. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
PAVANELLO, Marcelo Antonio et al. Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., & Claeys, C. (2005). Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Simoen E, Claeys C. Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Vancouver
Pavanello MA, Martino JA, Simoen E, Claeys C. Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Trabalho de evento
Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments (2005)
Pavanello, Marcelo Antonio ; Cerdeira, Antonio ; Martino, João Antonio ; Alemán, Miguel A; Flandre, Denis
Fonte: Microelectronics Technology and Devices SBMICRO 2005. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
PAVANELLO, Marcelo Antonio et al. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Cerdeira, A., Martino, J. A., Alemán, M. A., & Flandre, D. (2005). Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Vancouver
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Trabalho de evento
Simple method to determine the poly gate doping concentration based on poly depletion effect (2005)
Rodrigues, Michele; Sonnenberg, Victor ; Martino, João Antonio
Fonte: Proceedings v. 2005-08. Microelectronics Technology and Devices SBMICRO 2005. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
RODRIGUES, Michele e SONNENBERG, Victor e MARTINO, João Antonio. Simple method to determine the poly gate doping concentration based on poly depletion effect. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 15 nov. 2025.
APA
Rodrigues, M., Sonnenberg, V., & Martino, J. A. (2005). Simple method to determine the poly gate doping concentration based on poly depletion effect. In Proceedings v. 2005-08. Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Rodrigues M, Sonnenberg V, Martino JA. Simple method to determine the poly gate doping concentration based on poly depletion effect. Proceedings v. 2005-08. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Vancouver
Rodrigues M, Sonnenberg V, Martino JA. Simple method to determine the poly gate doping concentration based on poly depletion effect. Proceedings v. 2005-08. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Trabalho de evento
Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range (2005)
Gimenez, Salvador Pinillos ; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Fonte: Microelectronics Technology and Devices SBMICRO 2005. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
GIMENEZ, Salvador Pinillos et al. Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 15 nov. 2025.
APA
Gimenez, S. P., Pavanello, M. A., Martino, J. A., & Flandre, D. (2005). Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Gimenez SP, Pavanello MA, Martino JA, Flandre D. Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Vancouver
Gimenez SP, Pavanello MA, Martino JA, Flandre D. Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Trabalho de evento
Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs (2005)
Galeti, Milene; Claeys, Cor ; Martino, João Antonio ; Simoen, Eddy
Fonte: Microelectronics Technology and Devices SBMICRO 2005. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
GALETI, Milene et al. Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 15 nov. 2025.
APA
Galeti, M., Claeys, C., Martino, J. A., & Simoen, E. (2005). Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Galeti M, Claeys C, Martino JA, Simoen E. Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Vancouver
Galeti M, Claeys C, Martino JA, Simoen E. Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2025 nov. 15 ]
Trabalho de evento
Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures (2004)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
PAVANELLO, Marcelo Antonio et al. Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., & Claeys, C. (2004). Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. In Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Simoen E, Claeys C. Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. 2004 ;[citado 2025 nov. 15 ]
Vancouver
Pavanello MA, Martino JA, Simoen E, Claeys C. Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. 2004 ;[citado 2025 nov. 15 ]
Trabalho de evento
Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures (2004)
Pavanello, Marcelo Antonio ; Cerdeira, Antonio ; Martino, João Antonio ; Alemán, Miguel A; Flandre, Denis
Fonte: Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Cerdeira, A., Martino, J. A., Alemán, M. A., & Flandre, D. (2004). Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. In Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2025 nov. 15 ]
Vancouver
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2025 nov. 15 ]
Trabalho de evento
Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures (2004)
Santos, Carolina Davanzzo Gomes dos; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis ; Raskin, Jean-Pierre
Fonte: Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SANTOS, Carolina Davanzzo Gomes dos et al. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 15 nov. 2025.
APA
Santos, C. D. G. dos, Pavanello, M. A., Martino, J. A., Flandre, D., & Raskin, J. -P. (2004). Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. In Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. Pennington: The Electrochemical Society.
NLM
Santos CDG dos, Pavanello MA, Martino JA, Flandre D, Raskin J-P. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2025 nov. 15 ]
Vancouver
Santos CDG dos, Pavanello MA, Martino JA, Flandre D, Raskin J-P. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2025 nov. 15 ]
Parte de monografia/livro
Determination of the silicon film thickness and back oxide charge density on graded-channel SOI nMOSFETs (2003)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Pavanello, Marcelo Antonio
Fonte: Microelectronic Technology and Devices SBMicro 2003. Nome do evento: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
NICOLETT, Aparecido Sirley e MARTINO, João Antonio e PAVANELLO, Marcelo Antonio. Determination of the silicon film thickness and back oxide charge density on graded-channel SOI nMOSFETs. Microelectronic Technology and Devices SBMicro 2003. Tradução . Pennington: Electrochemical Society, 2003. . . Acesso em: 15 nov. 2025.
APA
Nicolett, A. S., Martino, J. A., & Pavanello, M. A. (2003). Determination of the silicon film thickness and back oxide charge density on graded-channel SOI nMOSFETs. In Microelectronic Technology and Devices SBMicro 2003. Pennington: Electrochemical Society.
NLM
Nicolett AS, Martino JA, Pavanello MA. Determination of the silicon film thickness and back oxide charge density on graded-channel SOI nMOSFETs. In: Microelectronic Technology and Devices SBMicro 2003. Pennington: Electrochemical Society; 2003. [citado 2025 nov. 15 ]
Vancouver
Nicolett AS, Martino JA, Pavanello MA. Determination of the silicon film thickness and back oxide charge density on graded-channel SOI nMOSFETs. In: Microelectronic Technology and Devices SBMicro 2003. Pennington: Electrochemical Society; 2003. [citado 2025 nov. 15 ]

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