Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures (2004)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2004
- Source:
- Título do periódico: Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
PAVANELLO, Marcelo Antonio et al. Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 18 set. 2024. -
APA
Pavanello, M. A., Martino, J. A., Simoen, E., & Claeys, C. (2004). Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. In Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Martino JA, Simoen E, Claeys C. Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. 2004 ;[citado 2024 set. 18 ] -
Vancouver
Pavanello MA, Martino JA, Simoen E, Claeys C. Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. 2004 ;[citado 2024 set. 18 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Comparison between 0.13Mm partially-depleted silicon-on-insulator technology with floating body operation at 300 K and 90 K
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
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