Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures (2004)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2004
- Source:
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
SANTOS, Carolina Davanzzo Gomes dos et al. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 05 jan. 2026. -
APA
Santos, C. D. G. dos, Pavanello, M. A., Martino, J. A., Flandre, D., & Raskin, J. -P. (2004). Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. In Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. Pennington: The Electrochemical Society. -
NLM
Santos CDG dos, Pavanello MA, Martino JA, Flandre D, Raskin J-P. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2026 jan. 05 ] -
Vancouver
Santos CDG dos, Pavanello MA, Martino JA, Flandre D, Raskin J-P. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2026 jan. 05 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
- Low temperature operation of graded-channel SOI nMOSFETs for analog applications
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