Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures (2004)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- School: EP
- Subject: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Place of publication: Pennington
- Date published: 2004
- Source:
- Título do periódico: Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03
- Conference title: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
SANTOS, Carolina Davanzzo Gomes dos et al. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 09 ago. 2022. -
APA
Santos, C. D. G. dos, Pavanello, M. A., Martino, J. A., Flandre, D., & Raskin, J. -P. (2004). Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. In Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. Pennington: The Electrochemical Society. -
NLM
Santos CDG dos, Pavanello MA, Martino JA, Flandre D, Raskin J-P. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2022 ago. 09 ] -
Vancouver
Santos CDG dos, Pavanello MA, Martino JA, Flandre D, Raskin J-P. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2022 ago. 09 ] - Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K
- Determination of the silicon film thickness and back oxide charge density on graded-channel SOI nMOSFETs
- A physically-based continuous model for graded-channel SOI MOSFET
- Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape
- Comparison between 0.13Mm partially-depleted silicon-on-insulator technology with floating body operation at 300 K and 90 K
- Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor
How to cite
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
