Low temperature operation of graded-channel SOI nMOSFETs for analog applications (2002)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- School: EP
- DOI: 10.1051/jp420020030
- Subject: CIRCUITOS INTEGRADOS MOS
- Language: Inglês
- Imprenta:
- Source:
- Título do periódico: Journal de Physique IV
- ISSN: 0036-827X
- Volume/Número/Paginação/Ano: v.12, n.3, may 2002
- Este periódico é de assinatura
- Este artigo NÃO é de acesso aberto
- Cor do Acesso Aberto: closed
-
ABNT
PAVANELLO, Marcelo Antonio; AGOPIAN, Paula Ghedini Der; MARTINO, João Antonio; FLANDRE, Denis. Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, Paris, v. 12, n. 3, 2002. DOI: 10.1051/jp420020030. -
APA
Pavanello, M. A., Agopian, P. G. D., Martino, J. A., & Flandre, D. (2002). Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, 12( 3). doi:10.1051/jp420020030 -
NLM
Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV. 2002 ;12( 3): -
Vancouver
Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV. 2002 ;12( 3): - Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K
- Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape
- Determination of the silicon film thickness and back oxide charge density on graded-channel SOI nMOSFETs
- A physically-based continuous model for graded-channel SOI MOSFET
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs
Informações sobre o DOI: 10.1051/jp420020030 (Fonte: oaDOI API)
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