Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point (2008)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2008
- Source:
- Título: SBMICRO 2008: Anais
- ISSN: 1938-5862
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
CAMILLO, Luciano Mendes et al. Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point. 2008, Anais.. Pennington: The Electrochemical Society, 2008. . Acesso em: 14 fev. 2026. -
APA
Camillo, L. M., Martino, J. A., Simoen, E., & Claeys, C. (2008). Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point. In SBMICRO 2008: Anais. Pennington: The Electrochemical Society. -
NLM
Camillo LM, Martino JA, Simoen E, Claeys C. Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point. SBMICRO 2008: Anais. 2008 ;[citado 2026 fev. 14 ] -
Vancouver
Camillo LM, Martino JA, Simoen E, Claeys C. Influence of the drain bias and gate lenght of partially depleted SOI MOSFETs on the ZTC biasing point. SBMICRO 2008: Anais. 2008 ;[citado 2026 fev. 14 ] - Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance
- Caracterização elétrica de dispositivos SOI MOS em baixa temperatura
- Metodo simples para a obtencao da densidade de armadilhas na primeira e segunda interface em soi-mosfet
- Combined l and series resistance extraction of ldd mosfets
- Influencia da temperatura em transistores soi (silicon on insulator) mosfets
- Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k
- The impact of gate length scaling on UTBOX FDSOI devices: the digital/analog performance of extension-less structures
- Simple method for the determination of the interface trap density at 77k in fully depleted acumulation mode soi mosfets
- Transistor soi-nmosfet nao auto-alinhado
- Impact of selective epitaxial growth and uniaxial/biaxial strain on DIBL effect using triple gate FinFETs
How to cite
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
