Physical characterization and reliability aspects of MuGFETs (2007)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2007
- Source:
- Título: SBMicro 2007
- ISSN: 1938-5862
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
CLAEYS, Cor et al. Physical characterization and reliability aspects of MuGFETs. 2007, Anais.. Pennington: The Electrochemical Society, 2007. . Acesso em: 18 fev. 2026. -
APA
Claeys, C., Simoen, E., Rafi, J. M., Pavanello, M. A., & Martino, J. A. (2007). Physical characterization and reliability aspects of MuGFETs. In SBMicro 2007. Pennington: The Electrochemical Society. -
NLM
Claeys C, Simoen E, Rafi JM, Pavanello MA, Martino JA. Physical characterization and reliability aspects of MuGFETs. SBMicro 2007. 2007 ;[citado 2026 fev. 18 ] -
Vancouver
Claeys C, Simoen E, Rafi JM, Pavanello MA, Martino JA. Physical characterization and reliability aspects of MuGFETs. SBMicro 2007. 2007 ;[citado 2026 fev. 18 ] - Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
- Analysis on GC SOI MOSFET analog parameters at high temperatures
- Operation of double gate graded-channel transistors at low temperatures
- Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
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