ReP USP - Resultado da busca

Artigo de periodico
Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor (2005)
Cerdeira, Antonio ; Alemán, Miguel A.; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis ; Vancaillie, Laurent
Source: IEEE Transactions on Electron Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
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ABNT
CERDEIRA, Antonio et al. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, v. 52, n. 5, p. 967-972, 2005Tradução . . Disponível em: https://doi.org/10.1109/ted.2005.846327. Acesso em: 04 out. 2024.
APA
Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Flandre, D., & Vancaillie, L. (2005). Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, 52( 5), 967-972. doi:10.1109/ted.2005.846327
NLM
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2024 out. 04 ] Available from: https://doi.org/10.1109/ted.2005.846327
Vancouver
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2024 out. 04 ] Available from: https://doi.org/10.1109/ted.2005.846327
Artigo de periodico
SOI technology characterization using SOI-MOS capacitor (2005)
Sonnenberg, Victor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SONNENBERG, Victor e MARTINO, João Antonio. SOI technology characterization using SOI-MOS capacitor. Solid-State Electronics, 2005Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2004.06.010. Acesso em: 04 out. 2024.
APA
Sonnenberg, V., & Martino, J. A. (2005). SOI technology characterization using SOI-MOS capacitor. Solid-State Electronics. doi:10.1016/j.sse.2004.06.010
NLM
Sonnenberg V, Martino JA. SOI technology characterization using SOI-MOS capacitor [Internet]. Solid-State Electronics. 2005 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/j.sse.2004.06.010
Vancouver
Sonnenberg V, Martino JA. SOI technology characterization using SOI-MOS capacitor [Internet]. Solid-State Electronics. 2005 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/j.sse.2004.06.010
Artigo de periodico
Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures (2004)
Bellodi, Marcello; Martino, João Antonio
Source: Journal Integrated Circuits and Systems. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
BELLODI, Marcello e MARTINO, João Antonio. Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures. Journal Integrated Circuits and Systems, v. 1, n. 2, p. 31-35, 2004Tradução . . Disponível em: https://doi.org/10.29292/jics.v1i2.261. Acesso em: 04 out. 2024.
APA
Bellodi, M., & Martino, J. A. (2004). Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures. Journal Integrated Circuits and Systems, 1( 2), 31-35. doi:10.29292/jics.v1i2.261
NLM
Bellodi M, Martino JA. Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures [Internet]. Journal Integrated Circuits and Systems. 2004 ;1( 2): 31-35.[citado 2024 out. 04 ] Available from: https://doi.org/10.29292/jics.v1i2.261
Vancouver
Bellodi M, Martino JA. Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures [Internet]. Journal Integrated Circuits and Systems. 2004 ;1( 2): 31-35.[citado 2024 out. 04 ] Available from: https://doi.org/10.29292/jics.v1i2.261
Artigo de periodico
Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body (2002)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Mercha, A.; Rafi, J.M.; Simoen, Eddy ; Claeys, Cor ; Van Meer, H.; De Meyer, K.
Source: Journal de Physique IV. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
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ABNT
PAVANELLO, Marcelo Antonio et al. Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, v. 12, n. 3, 2002Tradução . . Acesso em: 04 out. 2024.
APA
Pavanello, M. A., Martino, J. A., Mercha, A., Rafi, J. M., Simoen, E., Claeys, C., et al. (2002). Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, 12( 3).
NLM
Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2024 out. 04 ]
Vancouver
Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2024 out. 04 ]
Artigo de periodico
Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices (2002)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: FILMES FINOS
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ABNT
NICOLETT, Aparecido Sirley et al. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices. Solid-State Electronics, n. 9, p. 1381-1387, 2002Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(02)00067-9. Acesso em: 04 out. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2002). Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices. Solid-State Electronics, ( 9), 1381-1387. doi:10.1016/s0038-1101(02)00067-9
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices [Internet]. Solid-State Electronics. 2002 ;( 9): 1381-1387.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(02)00067-9
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices [Internet]. Solid-State Electronics. 2002 ;( 9): 1381-1387.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(02)00067-9
Artigo de periodico
Low temperature operation of graded-channel SOI nMOSFETs for analog applications (2002)
Pavanello, Marcelo Antonio ; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Flandre, Denis
Source: Journal de Physique IV. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, v. 12, n. 3, 2002Tradução . . Disponível em: https://doi.org/10.1051/jp420020030. Acesso em: 04 out. 2024.
APA
Pavanello, M. A., Agopian, P. G. D., Martino, J. A., & Flandre, D. (2002). Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, 12( 3). doi:10.1051/jp420020030
NLM
Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications [Internet]. Journal de Physique IV. 2002 ;12( 3):[citado 2024 out. 04 ] Available from: https://doi.org/10.1051/jp420020030
Vancouver
Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications [Internet]. Journal de Physique IV. 2002 ;12( 3):[citado 2024 out. 04 ] Available from: https://doi.org/10.1051/jp420020030
Artigo de periodico
Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, v. No 2000, n. 11, p. 1961-1969, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00166-0. Acesso em: 04 out. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, No 2000( 11), 1961-1969. doi:10.1016/s0038-1101(00)00166-0
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Artigo de periodico
Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, v. 44, n. 6, p. 917-922, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00032-0. Acesso em: 04 out. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44( 6), 917-922. doi:10.1016/s0038-1101(00)00032-0
NLM
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0
Vancouver
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0
Artigo de periodico
An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis
Source: Electrochemical and Solid-State Letters. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
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ABNT
PAVANELLO, Marcelo Antonio et al. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, v. 3, n. Ja 2000, p. 50-52, 2000Tradução . . Disponível em: https://doi.org/10.1149/1.1390955. Acesso em: 04 out. 2024.
APA
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, 3( Ja 2000), 50-52. doi:10.1149/1.1390955
NLM
Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2024 out. 04 ] Available from: https://doi.org/10.1149/1.1390955
Vancouver
Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2024 out. 04 ] Available from: https://doi.org/10.1149/1.1390955
Artigo de periodico
Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, v. 44, n. 4, p. 677-684, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00293-2. Acesso em: 04 out. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, 44( 4), 677-684. doi:10.1016/s0038-1101(99)00293-2
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2
Artigo de periodico
Leakage drain current behavior in an accumulation mode SOI p-channel MOSFET operating at high temperatures (1999)
Bellodi, Marcello; Martino, João Antonio
Source: Electrochemical and Solid State Letters. Unidade: EP
Assunto: ELETROQUÍMICA
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ABNT
BELLODI, Marcello e MARTINO, João Antonio. Leakage drain current behavior in an accumulation mode SOI p-channel MOSFET operating at high temperatures. Electrochemical and Solid State Letters, v. 2, n. 7, p. 345-346, 1999Tradução . . Disponível em: https://doi.org/10.1149/1.1390831. Acesso em: 04 out. 2024.
APA
Bellodi, M., & Martino, J. A. (1999). Leakage drain current behavior in an accumulation mode SOI p-channel MOSFET operating at high temperatures. Electrochemical and Solid State Letters, 2( 7), 345-346. doi:10.1149/1.1390831
NLM
Bellodi M, Martino JA. Leakage drain current behavior in an accumulation mode SOI p-channel MOSFET operating at high temperatures [Internet]. Electrochemical and Solid State Letters. 1999 ; 2( 7): 345-346.[citado 2024 out. 04 ] Available from: https://doi.org/10.1149/1.1390831
Vancouver
Bellodi M, Martino JA. Leakage drain current behavior in an accumulation mode SOI p-channel MOSFET operating at high temperatures [Internet]. Electrochemical and Solid State Letters. 1999 ; 2( 7): 345-346.[citado 2024 out. 04 ] Available from: https://doi.org/10.1149/1.1390831
Artigo de periodico
Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction (1999)
Sonnenberg, Victor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SONNENBERG, Victor e MARTINO, João Antonio. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction. Solid-State Electronics, 1999Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00191-4. Acesso em: 04 out. 2024.
APA
Sonnenberg, V., & Martino, J. A. (1999). Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction. Solid-State Electronics. doi:10.1016/s0038-1101(99)00191-4
NLM
Sonnenberg V, Martino JA. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction [Internet]. Solid-State Electronics. 1999 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00191-4
Vancouver
Sonnenberg V, Martino JA. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction [Internet]. Solid-State Electronics. 1999 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00191-4
Artigo de periodico
A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature (1999)
Sonnenberg, Victor ; Martino, João Antonio
Source: Electrochemical and Solid-State Letters. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SONNENBERG, Victor e MARTINO, João Antonio. A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature. Electrochemical and Solid-State Letters, v. 2, n. 11, p. 585-586, 1999Tradução . . Acesso em: 04 out. 2024.
APA
Sonnenberg, V., & Martino, J. A. (1999). A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature. Electrochemical and Solid-State Letters, 2( 11), 585-586.
NLM
Sonnenberg V, Martino JA. A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature. Electrochemical and Solid-State Letters. 1999 ;2( 11): 585-586.[citado 2024 out. 04 ]
Vancouver
Sonnenberg V, Martino JA. A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature. Electrochemical and Solid-State Letters. 1999 ;2( 11): 585-586.[citado 2024 out. 04 ]
Artigo de periodico
Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's (1999)
Pavanello, Marcelo Antonio ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics, 1999Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00178-1. Acesso em: 04 out. 2024.
APA
Pavanello, M. A., & Martino, J. A. (1999). Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics. doi:10.1016/s0038-1101(99)00178-1
NLM
Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1
Vancouver
Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1
Artigo de periodico
Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k (1997)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Source: Microelectronic Engineering. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, v. 36, n. 1-4, p. 375-378, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0167-9317(97)00083-x. Acesso em: 04 out. 2024.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, 36( 1-4), 375-378. doi:10.1016/s0167-9317(97)00083-x
NLM
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x

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