Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k (1997)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- DOI: 10.1016/s0167-9317(97)00083-x
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Source:
- Título: Microelectronic Engineering
- ISSN: 0167-9317
- Volume/Número/Paginação/Ano: v. 36, n.1-4, p. 375-378, June 1997
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, v. 36, n. 1-4, p. 375-378, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0167-9317(97)00083-x. Acesso em: 19 jan. 2026. -
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, 36( 1-4), 375-378. doi:10.1016/s0167-9317(97)00083-x -
NLM
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2026 jan. 19 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x -
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2026 jan. 19 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x - Analog performance and application of graded-channel fully depleted SOI MOSFETs
- Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects
- Projeto de processos de fabricação avançados aplicáveis nas tecnologias CMOS micrométricas
- Simple method to determine the poly gate doping concentration based on poly depletion effect
- A new technique to extract the oxide charge density at front and back interfaces of SOI nMOSFETs devices
- Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET
- A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region
- A simple method to model nonrectangular-gate layout in SOI MOSFETs
- New leakage drain current model for high temperature soi mesfet
- Influence of the substrate potential drop on fully depleted soi mesfet threshold voltage at 77k
Informações sobre o DOI: 10.1016/s0167-9317(97)00083-x (Fonte: oaDOI API)
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