Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body (2002)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS MOS
- Language: Inglês
- Imprenta:
- Source:
- Título: Journal de Physique IV
- ISSN: 0036-827X
- Volume/Número/Paginação/Ano: v.12, n.3, may 2002
-
ABNT
PAVANELLO, Marcelo Antonio et al. Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, v. 12, n. 3, 2002Tradução . . Acesso em: 13 fev. 2026. -
APA
Pavanello, M. A., Martino, J. A., Mercha, A., Rafi, J. M., Simoen, E., Claeys, C., et al. (2002). Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, 12( 3). -
NLM
Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2026 fev. 13 ] -
Vancouver
Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2026 fev. 13 ] - Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance
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- Influencia da temperatura em transistores soi (silicon on insulator) mosfets
- Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k
- The impact of gate length scaling on UTBOX FDSOI devices: the digital/analog performance of extension-less structures
- Simple method for the determination of the interface trap density at 77k in fully depleted acumulation mode soi mosfets
- Transistor soi-nmosfet nao auto-alinhado
- Impact of selective epitaxial growth and uniaxial/biaxial strain on DIBL effect using triple gate FinFETs
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