Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor (2005)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- DOI: 10.1109/ted.2005.846327
- Assunto: CIRCUITOS INTEGRADOS MOS
- Language: Inglês
- Imprenta:
- Source:
- Título: IEEE Transactions on Electron Devices
- ISSN: 0018-9383
- Volume/Número/Paginação/Ano: v.52, n.5, p.967-972, 2005
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
CERDEIRA, Antonio et al. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, v. 52, n. 5, p. 967-972, 2005Tradução . . Disponível em: https://doi.org/10.1109/ted.2005.846327. Acesso em: 10 fev. 2026. -
APA
Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Flandre, D., & Vancaillie, L. (2005). Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, 52( 5), 967-972. doi:10.1109/ted.2005.846327 -
NLM
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2026 fev. 10 ] Available from: https://doi.org/10.1109/ted.2005.846327 -
Vancouver
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2026 fev. 10 ] Available from: https://doi.org/10.1109/ted.2005.846327 - Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
- Analysis on GC SOI MOSFET analog parameters at high temperatures
- Operation of double gate graded-channel transistors at low temperatures
- Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
Informações sobre o DOI: 10.1109/ted.2005.846327 (Fonte: oaDOI API)
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