A new method for determination of the fixed charge density at the buried oxide/underlying substrate interface in SOI MOSFETs (1997)
- Authors:
- USP affiliated author: MARTINO, JOAO ANTONIO - EP
- School: EP
- Subjects: MICROELETRÔNICA; CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Place of publication: Pennington
- Date published: 1997
- Source:
- Título do periódico: Proceedings 3. Symposium on Silicon-on-Insulator Technology and Devices
- Conference title: Symposium Silicon-on-Insulator Technology and Devices
-
ABNT
PAVANELLO, Marcelo Antonio; MARTINO, João Antonio. A new method for determination of the fixed charge density at the buried oxide/underlying substrate interface in SOI MOSFETs. In: Proceedings 3. Symposium on Silicon-on-Insulator Technology and Devices[S.l: s.n.], 1997. -
APA
Pavanello, M. A., & Martino, J. A. (1997). A new method for determination of the fixed charge density at the buried oxide/underlying substrate interface in SOI MOSFETs. In Proceedings 3. Symposium on Silicon-on-Insulator Technology and Devices. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Martino JA. A new method for determination of the fixed charge density at the buried oxide/underlying substrate interface in SOI MOSFETs. In: Proceedings 3. Symposium on Silicon-on-Insulator Technology and Devices. Pennington: The Electrochemical Society; 1997. -
Vancouver
Pavanello MA, Martino JA. A new method for determination of the fixed charge density at the buried oxide/underlying substrate interface in SOI MOSFETs. In: Proceedings 3. Symposium on Silicon-on-Insulator Technology and Devices. Pennington: The Electrochemical Society; 1997. - Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs
- Caracterização elétrica de dispositivos SOI MOS em baixa temperatura
- Projeto de processos de fabricação avançados aplicáveis nas tecnologias CMOS micrométricas
- Analysis of the linear kink effect in partially depleted SOI nMOSFETs
- Low-Frequency noise behaviour of bulk and DTMOS triple-gate devices under 60 MeV proton irradiaton
- Low frequency noise assessment in advanced UTBOX SOI n-channel MOSFETs
- Low-Frequency Noise Studies on Fully Depleted UTBOX Silicon-on-Insulator nMOSFETs: Challenges and Opportunities
- Understanding and optimizing the floating body retention in FDSOI UTBOX
- Halo optimization for 0.13 micron SOI CMOS technology
- Analog performance of dynamic threshold voltage SOI MOSFET
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