Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs (2004)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- Subjects: MICROELETRÔNICA; CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2004
- Source:
- Conference titles: Symposium on High Purity Silicon
-
ABNT
MARTINO, João Antonio et al. Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. 8. Symposium on High Purity Silicon: proceedings. Tradução . Pennington: The Electrochemical Society, 2004. . . Acesso em: 10 jan. 2026. -
APA
Martino, J. A., Rafi, J. M., Mercha, A., Simoen, E., & Claeys, C. (2004). Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. In 8. Symposium on High Purity Silicon: proceedings. Pennington: The Electrochemical Society. -
NLM
Martino JA, Rafi JM, Mercha A, Simoen E, Claeys C. Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. In: 8. Symposium on High Purity Silicon: proceedings. Pennington: The Electrochemical Society; 2004. [citado 2026 jan. 10 ] -
Vancouver
Martino JA, Rafi JM, Mercha A, Simoen E, Claeys C. Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. In: 8. Symposium on High Purity Silicon: proceedings. Pennington: The Electrochemical Society; 2004. [citado 2026 jan. 10 ] - TCAD Strain Calibration Versus Nanobeam Diffraction of Source/Drain Stressors for Ge MOSFETs
- Carriers mobility extraction methods for triple-gate FinFET
- Analysis of the linear kink effect in partially depleted SOI nMOSFETs
- Simple method to extract the length dependent mobility degradation factor at 77 K
- Low temperature and channel engineering influence on harmonic distortion of soi nmosfets for analog applications
- Analysis of the capacitance vs. voltage in graded channel SOI capacitor
- The graded-channel SOI MOSFET to alleviate the parasitic bipolar effects and improve the output characteristics
- Projeto de processos de fabricação avançados aplicáveis nas tecnologias CMOS micrométricas
- Proposta de uma sequência simples de fabricação de circuitos integrados digitais NMOS com carga em depleção e porta de silício policristalino
- Um processo CMOS de cavidade dupla para comprimento de porta de 2µm
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