Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs (2004)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- Subjects: MICROELETRÔNICA; CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2004
- Source:
- Conference titles: Symposium on High Purity Silicon
-
ABNT
MARTINO, João Antonio et al. Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. 8. Symposium on High Purity Silicon: proceedings. Tradução . Pennington: The Electrochemical Society, 2004. . . Acesso em: 15 mar. 2026. -
APA
Martino, J. A., Rafi, J. M., Mercha, A., Simoen, E., & Claeys, C. (2004). Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. In 8. Symposium on High Purity Silicon: proceedings. Pennington: The Electrochemical Society. -
NLM
Martino JA, Rafi JM, Mercha A, Simoen E, Claeys C. Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. In: 8. Symposium on High Purity Silicon: proceedings. Pennington: The Electrochemical Society; 2004. [citado 2026 mar. 15 ] -
Vancouver
Martino JA, Rafi JM, Mercha A, Simoen E, Claeys C. Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. In: 8. Symposium on High Purity Silicon: proceedings. Pennington: The Electrochemical Society; 2004. [citado 2026 mar. 15 ] - Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance
- Caracterização elétrica de dispositivos SOI MOS em baixa temperatura
- Metodo simples para a obtencao da densidade de armadilhas na primeira e segunda interface em soi-mosfet
- Combined l and series resistance extraction of ldd mosfets
- Influencia da temperatura em transistores soi (silicon on insulator) mosfets
- Impact of substrate effect on the fully depleted soi mesfet subthreshold slope at 300k and 77k
- The impact of gate length scaling on UTBOX FDSOI devices: the digital/analog performance of extension-less structures
- Simple method for the determination of the interface trap density at 77k in fully depleted acumulation mode soi mosfets
- Transistor soi-nmosfet nao auto-alinhado
- Impact of selective epitaxial growth and uniaxial/biaxial strain on DIBL effect using triple gate FinFETs
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