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Artigo de periodico
ISFET fabrication and characterization for hydrogen peroxide sensing (2023)
Duarte, Pedro Henrique; Rangel, Ricardo Cardoso; Ramos, Daniel Augusto; Yojo, Leonardo Shimizu; Mori, Carlos Augusto Bergfeld; Sasaki, Katia Regina Akemi; Agopian, Paula Ghedini Der ; Martino, João Antonio
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assuntos: TRANSISTORES, SOLUÇÕES
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ABNT
DUARTE, Pedro Henrique et al. ISFET fabrication and characterization for hydrogen peroxide sensing. Journal of Integrated Circuits and Systems, v. 18, n. 1, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.29292/jics.v18i1.646. Acesso em: 16 nov. 2025.
APA
Duarte, P. H., Rangel, R. C., Ramos, D. A., Yojo, L. S., Mori, C. A. B., Sasaki, K. R. A., et al. (2023). ISFET fabrication and characterization for hydrogen peroxide sensing. Journal of Integrated Circuits and Systems, 18( 1), 1-4. doi:10.29292/jics.v18i1.646
NLM
Duarte PH, Rangel RC, Ramos DA, Yojo LS, Mori CAB, Sasaki KRA, Agopian PGD, Martino JA. ISFET fabrication and characterization for hydrogen peroxide sensing [Internet]. Journal of Integrated Circuits and Systems. 2023 ; 18( 1): 1-4.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v18i1.646
Vancouver
Duarte PH, Rangel RC, Ramos DA, Yojo LS, Mori CAB, Sasaki KRA, Agopian PGD, Martino JA. ISFET fabrication and characterization for hydrogen peroxide sensing [Internet]. Journal of Integrated Circuits and Systems. 2023 ; 18( 1): 1-4.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v18i1.646
Artigo de periodico
Fractional-order MOS capacitor: experimental results and Monte Carlo analysis (2023)
Fernandes, Lucas Almir dos Santos; Alayo Chávez, Marco Isaías ; Martino, João Antonio
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assuntos: FRACTAIS, SIMULAÇÃO, AVALIAÇÃO DE DESEMPENHO
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ABNT
FERNANDES, Lucas Almir dos Santos e ALAYO CHÁVEZ, Marco Isaías e MARTINO, João Antonio. Fractional-order MOS capacitor: experimental results and Monte Carlo analysis. Journal of Integrated Circuits and Systems, v. 18, n. 1, p. 1-5, 2023Tradução . . Disponível em: https://doi.org/10.29292/jics.v18i1.660. Acesso em: 16 nov. 2025.
APA
Fernandes, L. A. dos S., Alayo Chávez, M. I., & Martino, J. A. (2023). Fractional-order MOS capacitor: experimental results and Monte Carlo analysis. Journal of Integrated Circuits and Systems, 18( 1), 1-5. doi:10.29292/jics.v18i1.660
NLM
Fernandes LA dos S, Alayo Chávez MI, Martino JA. Fractional-order MOS capacitor: experimental results and Monte Carlo analysis [Internet]. Journal of Integrated Circuits and Systems. 2023 ; 18( 1): 1-5.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v18i1.660
Vancouver
Fernandes LA dos S, Alayo Chávez MI, Martino JA. Fractional-order MOS capacitor: experimental results and Monte Carlo analysis [Internet]. Journal of Integrated Circuits and Systems. 2023 ; 18( 1): 1-5.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v18i1.660
Artigo de periodico
Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data (2023)
Toledo, Rodrigo do Nascimento; Martino, João Antonio ; Agopian, Paula Ghedini Der
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assuntos: TRANSISTORES, CIRCUITOS ANALÓGICOS, NANOTECNOLOGIA
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ABNT
TOLEDO, Rodrigo do Nascimento e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data. Journal of Integrated Circuits and Systems, v. 18, n. 1, p. 1-6, 2023Tradução . . Disponível em: https://doi.org/10.29292/jics.v18i1.653. Acesso em: 16 nov. 2025.
APA
Toledo, R. do N., Martino, J. A., & Agopian, P. G. D. (2023). Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data. Journal of Integrated Circuits and Systems, 18( 1), 1-6. doi:10.29292/jics.v18il.653
NLM
Toledo R do N, Martino JA, Agopian PGD. Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data [Internet]. Journal of Integrated Circuits and Systems. 2023 ;18( 1): 1-6.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v18i1.653
Vancouver
Toledo R do N, Martino JA, Agopian PGD. Low-dropout voltage regulator designed with nanowire TFET with different source composition experimental data [Internet]. Journal of Integrated Circuits and Systems. 2023 ;18( 1): 1-6.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v18i1.653
Artigo de periodico
Reconfigurable SOI-MOSFET: past, present and future applications (2022)
Rangel, Ricardo Cardoso; Sasaki, Kátia Regina Akemi ; Martino, João Antonio
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assuntos: TRANSISTORES, SENSOR, CIRCUITOS INTEGRADOS MOS
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ABNT
RANGEL, Ricardo Cardoso e SASAKI, Kátia Regina Akemi e MARTINO, João Antonio. Reconfigurable SOI-MOSFET: past, present and future applications. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-9, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17i2.626. Acesso em: 16 nov. 2025.
APA
Rangel, R. C., Sasaki, K. R. A., & Martino, J. A. (2022). Reconfigurable SOI-MOSFET: past, present and future applications. Journal of Integrated Circuits and Systems, 17( 2), 1-9. doi:10.29292/jics.v17i2.626
NLM
Rangel RC, Sasaki KRA, Martino JA. Reconfigurable SOI-MOSFET: past, present and future applications [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-9.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v17i2.626
Vancouver
Rangel RC, Sasaki KRA, Martino JA. Reconfigurable SOI-MOSFET: past, present and future applications [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-9.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v17i2.626
Artigo de periodico
Tunnel-FET evolution and applications for analog circuits (2022)
Agopian, Paula Ghedini Der ; Martino, João Antonio ; Simoen, Eddy ; Rooyackers, Rita ; Claeys, Cor
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assuntos: TRANSISTORES, SENSOR, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS
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ABNT
AGOPIAN, Paula Ghedini Der et al. Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-7, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17i2.631. Acesso em: 16 nov. 2025.
APA
Agopian, P. G. D., Martino, J. A., Simoen, E., Rooyackers, R., & Claeys, C. (2022). Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, 17( 2), 1-7. doi:10.29292/jics.v17i2.631
NLM
Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v17i2.631
Vancouver
Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v17i2.631
Artigo de periodico
Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications (2022)
Simoen, Eddy ; Coelho, Carlos Henrique Santos; Silva, Vanessa Cristina Pereira da; Martino, João Antonio ; Agopian, Paula Ghedini Der ; Oliveira, Alberto; Cretu, Bogdan; Veloso, Anabela
Fonte: Journal of Integrated Circuits and Systems. Unidades: EP, EESC
Assuntos: TRANSISTORES, NANOELETRÔNICA, TEMPERATURA
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ABNT
SIMOEN, Eddy et al. Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-9, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17i2.617. Acesso em: 16 nov. 2025.
APA
Simoen, E., Coelho, C. H. S., Silva, V. C. P. da, Martino, J. A., Agopian, P. G. D., Oliveira, A., et al. (2022). Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications. Journal of Integrated Circuits and Systems, 17( 2), 1-9. doi:10.29292/jics.v17i2.617
NLM
Simoen E, Coelho CHS, Silva VCP da, Martino JA, Agopian PGD, Oliveira A, Cretu B, Veloso A. Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-9.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v17i2.617
Vancouver
Simoen E, Coelho CHS, Silva VCP da, Martino JA, Agopian PGD, Oliveira A, Cretu B, Veloso A. Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-9.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v17i2.617
Artigo de periodico
Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C (2022)
Silva, Vanessa Cristina Pereira da; Leal, João Vitor da Costa; Perina, Welder F; Martino, João Antonio ; Simoen, Eddy ; Veloso, A; Agopian, Paula Ghedini Der
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assuntos: TRANSISTORES, NANOTECNOLOGIA, BAIXA TEMPERATURA
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ABNT
SILVA, Vanessa Cristina Pereira da et al. Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C. Journal of Integrated Circuits and Systems, v. 17, n. 1, p. 1-6, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17il.550. Acesso em: 16 nov. 2025.
APA
Silva, V. C. P. da, Leal, J. V. da C., Perina, W. F., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2022). Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C. Journal of Integrated Circuits and Systems, 17( 1), 1-6. doi:10.29292/jics.v17i1.550
NLM
Silva VCP da, Leal JV da C, Perina WF, Martino JA, Simoen E, Veloso A, Agopian PGD. Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C [Internet]. Journal of Integrated Circuits and Systems. 2022 ;17( 1): 1-6.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v17il.550
Vancouver
Silva VCP da, Leal JV da C, Perina WF, Martino JA, Simoen E, Veloso A, Agopian PGD. Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C [Internet]. Journal of Integrated Circuits and Systems. 2022 ;17( 1): 1-6.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v17il.550
Artigo de periodico
Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies (2017)
Itocazu, Vitor Tatsuo ; Sonnenberg, Victor ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: SEMICONDUTORES
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ABNT
ITOCAZU, Vitor Tatsuo et al. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems, v. 12, n. 2, p. 82-88, 2017Tradução . . Disponível em: https://doi.org/10.29292/jics.v12i2.455. Acesso em: 16 nov. 2025.
APA
Itocazu, V. T., Sonnenberg, V., Martino, J. A., Simoen, E., & Claeys, C. (2017). Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems, 12( 2), 82-88. doi:10.29292/jics.v12i2.455
NLM
Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies [Internet]. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v12i2.455
Vancouver
Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies [Internet]. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v12i2.455
Artigo de periodico
Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation (2016)
Itocazu, Vitor Tatsuo ; Martino, João Antonio ; Sasaki, Kátia Regina Akemi; Simoen, Eddy ; Claeys, Cor ; Sonnenberg, Victor
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: SEMICONDUTORES
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ABNT
ITOCAZU, Vitor Tatsuo et al. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems, v. 12, n. 2, p. 101-106, 2016Tradução . . Disponível em: https://doi.org/10.29292/jics.v12i2.458. Acesso em: 16 nov. 2025.
APA
Itocazu, V. T., Martino, J. A., Sasaki, K. R. A., Simoen, E., Claeys, C., & Sonnenberg, V. (2016). Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems, 12( 2), 101-106. doi:10.29292/jics.v12i2.458
NLM
Itocazu VT, Martino JA, Sasaki KRA, Simoen E, Claeys C, Sonnenberg V. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation [Internet]. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v12i2.458
Vancouver
Itocazu VT, Martino JA, Sasaki KRA, Simoen E, Claeys C, Sonnenberg V. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation [Internet]. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v12i2.458
Artigo de periodico
Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs (2014)
Teixeira, Fernando Ferrari; Martino, João Antonio ; Bordallo, Caio Cesar Mendes ; Silveira, Marcilei Aparecida Guazzelli da; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Claeys, Cor
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assuntos: MICROELETRÔNICA, RAIOS X
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ABNT
TEIXEIRA, Fernando Ferrari et al. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs. Journal of Integrated Circuits and Systems, v. 9, n. 2, p. 97-102, 2014Tradução . . Disponível em: https://doi.org/10.29292/jics.v9i2.394. Acesso em: 16 nov. 2025.
APA
Teixeira, F. F., Martino, J. A., Bordallo, C. C. M., Silveira, M. A. G. da, Agopian, P. G. D., Simoen, E., & Claeys, C. (2014). Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs. Journal of Integrated Circuits and Systems, 9( 2), 97-102. doi:10.29292/jics.v9i2.394
NLM
Teixeira FF, Martino JA, Bordallo CCM, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 97-102.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v9i2.394
Vancouver
Teixeira FF, Martino JA, Bordallo CCM, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 97-102.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v9i2.394
Artigo de periodico
Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results (2014)
Nissimoff, Albert; Claeys, Cor ; Aoulaiche, Marc; Sasaki, Karen Lucia Mayumi; Simoen, Eddy ; Martino, João Antonio
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
NISSIMOFF, Albert et al. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, v. 9, n. 2, p. 91-96, 2014Tradução . . Disponível em: https://doi.org/10.29292/jics.v9i2.393. Acesso em: 16 nov. 2025.
APA
Nissimoff, A., Claeys, C., Aoulaiche, M., Sasaki, K. L. M., Simoen, E., & Martino, J. A. (2014). Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, 9( 2), 91-96. doi:10.29292/jics.v9i2.393
NLM
Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v9i2.393
Vancouver
Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v9i2.393
Artigo de periodico
Nanowire Tunnel Field Effect Transistors at High Temperature (2013)
Martino, Márcio Dalla Valle; Neves, Felipe Souza; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Rooyackers, Rita; Claeys, Cor
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: NANOELETRÔNICA
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ABNT
MARTINO, Márcio Dalla Valle et al. Nanowire Tunnel Field Effect Transistors at High Temperature. Journal of Integrated Circuits and Systems, v. 8, n. 2, p. 110-115, 2013Tradução . . Disponível em: https://doi.org/10.29292/jics.v8i2.381. Acesso em: 16 nov. 2025.
APA
Martino, M. D. V., Neves, F. S., Agopian, P. G. D., Martino, J. A., Rooyackers, R., & Claeys, C. (2013). Nanowire Tunnel Field Effect Transistors at High Temperature. Journal of Integrated Circuits and Systems, 8( 2), 110-115. doi:10.29292/jics.v8i2.381
NLM
Martino MDV, Neves FS, Agopian PGD, Martino JA, Rooyackers R, Claeys C. Nanowire Tunnel Field Effect Transistors at High Temperature [Internet]. Journal of Integrated Circuits and Systems. 2013 ;8( 2): 110-115.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v8i2.381
Vancouver
Martino MDV, Neves FS, Agopian PGD, Martino JA, Rooyackers R, Claeys C. Nanowire Tunnel Field Effect Transistors at High Temperature [Internet]. Journal of Integrated Circuits and Systems. 2013 ;8( 2): 110-115.[citado 2025 nov. 16 ] Available from: https://doi.org/10.29292/jics.v8i2.381

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