Tunnel-FET evolution and applications for analog circuits (2022)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- DOI: 10.29292/jics.v17i2.631
- Subjects: TRANSISTORES; SENSOR; CIRCUITOS ANALÓGICOS; CIRCUITOS DIGITAIS
- Agências de fomento:
- Language: Inglês
- Imprenta:
- Publisher place: Porto Alegre
- Date published: 2022
- Source:
- Título: Journal of Integrated Circuits and Systems
- ISSN: 1807-1953
- Volume/Número/Paginação/Ano: v. 17, n. 2, p. 1-7, Oct. 2022
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
AGOPIAN, Paula Ghedini Der et al. Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-7, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17i2.631. Acesso em: 23 jan. 2026. -
APA
Agopian, P. G. D., Martino, J. A., Simoen, E., Rooyackers, R., & Claeys, C. (2022). Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, 17( 2), 1-7. doi:10.29292/jics.v17i2.631 -
NLM
Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2026 jan. 23 ] Available from: https://doi.org/10.29292/jics.v17i2.631 -
Vancouver
Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2026 jan. 23 ] Available from: https://doi.org/10.29292/jics.v17i2.631 - Analog circuit design using graded-channel SOI NMOSFETs
- Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures
- Extraction of the interface and oxide charge density in silicon-on-insulator MOSFETs
- Projeto de um processo CMOS com cavidade dupla e dimensões de porta de 2 um
- Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
- Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation
- Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results
- Estudo comparativo de estruturas de fonte e dreno de transistores mos submicrometricos
- Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices
- Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs
Informações sobre o DOI: 10.29292/jics.v17i2.631 (Fonte: oaDOI API)
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