Analysis of the series resistance and effective channel lenght extraction of submicron MOS transistors operating at high temperature. (em CD-Rom) (1997)
- Authors:
- Autor USP: MARTINO, JOAO ANTONIO - EP
- Unidade: EP
- Subjects: CIRCUITOS INTEGRADOS; SEMICONDUTORES
- Language: Inglês
- Imprenta:
- Publisher: SBMICRO/EFEI
- Publisher place: Itajubá
- Date published: 1997
- Source:
- Título: Proceedings
- Conference titles: Conference of the Brazilian Microelectronics Society
-
ABNT
NICOLETT, Aparecido Sirley e MARTINO, João Antonio e GUTIERREZ, E A. Analysis of the series resistance and effective channel lenght extraction of submicron MOS transistors operating at high temperature. (em CD-Rom). 1997, Anais.. Itajubá: SBMICRO/EFEI, 1997. . Acesso em: 26 jan. 2026. -
APA
Nicolett, A. S., Martino, J. A., & Gutierrez, E. A. (1997). Analysis of the series resistance and effective channel lenght extraction of submicron MOS transistors operating at high temperature. (em CD-Rom). In Proceedings. Itajubá: SBMICRO/EFEI. -
NLM
Nicolett AS, Martino JA, Gutierrez EA. Analysis of the series resistance and effective channel lenght extraction of submicron MOS transistors operating at high temperature. (em CD-Rom). Proceedings. 1997 ;[citado 2026 jan. 26 ] -
Vancouver
Nicolett AS, Martino JA, Gutierrez EA. Analysis of the series resistance and effective channel lenght extraction of submicron MOS transistors operating at high temperature. (em CD-Rom). Proceedings. 1997 ;[citado 2026 jan. 26 ] - Analog circuit design using graded-channel SOI NMOSFETs
- Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures
- Extraction of the interface and oxide charge density in silicon-on-insulator MOSFETs
- Projeto de um processo CMOS com cavidade dupla e dimensões de porta de 2 um
- Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
- Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation
- Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results
- Estudo comparativo de estruturas de fonte e dreno de transistores mos submicrometricos
- Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices
- Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs
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