New leakage drain current model for high temperature soi mesfet (1995)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Publisher: Instituto de Informatica da Ufrgs
- Publisher place: Porto Alegre
- Date published: 1995
- Source:
- Título: Proceedings
- Conference titles: Congress of the Brazilian Microelectronics Society
-
ABNT
BELLODI, Marcello e MARTINO, João Antonio e FLANDRE, M. New leakage drain current model for high temperature soi mesfet. 1995, Anais.. Porto Alegre: Instituto de Informatica da Ufrgs, 1995. . Acesso em: 20 jan. 2026. -
APA
Bellodi, M., Martino, J. A., & Flandre, M. (1995). New leakage drain current model for high temperature soi mesfet. In Proceedings. Porto Alegre: Instituto de Informatica da Ufrgs. -
NLM
Bellodi M, Martino JA, Flandre M. New leakage drain current model for high temperature soi mesfet. Proceedings. 1995 ;[citado 2026 jan. 20 ] -
Vancouver
Bellodi M, Martino JA, Flandre M. New leakage drain current model for high temperature soi mesfet. Proceedings. 1995 ;[citado 2026 jan. 20 ] - Analog performance and application of graded-channel fully depleted SOI MOSFETs
- Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects
- Projeto de processos de fabricação avançados aplicáveis nas tecnologias CMOS micrométricas
- Simple method to determine the poly gate doping concentration based on poly depletion effect
- A new technique to extract the oxide charge density at front and back interfaces of SOI nMOSFETs devices
- Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET
- A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region
- A simple method to model nonrectangular-gate layout in SOI MOSFETs
- Influence of the substrate potential drop on fully depleted soi mesfet threshold voltage at 77k
- A simple model for a new SOI MOSFET with asymmetric trapezoidal gate
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