Filtros : "Journal of Integrated Circuits and Systems" "Claeys, Cor" Limpar

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  • Fonte: Journal of Integrated Circuits and Systems. Unidade: EP

    Assuntos: TRANSISTORES, SENSOR, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS

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    • ABNT

      AGOPIAN, Paula Ghedini Der et al. Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-7, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17i2.631. Acesso em: 15 nov. 2025.
    • APA

      Agopian, P. G. D., Martino, J. A., Simoen, E., Rooyackers, R., & Claeys, C. (2022). Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, 17( 2), 1-7. doi:10.29292/jics.v17i2.631
    • NLM

      Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v17i2.631
    • Vancouver

      Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v17i2.631
  • Fonte: Journal of Integrated Circuits and Systems. Unidade: EP

    Assunto: SEMICONDUTORES

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    • ABNT

      ITOCAZU, Vitor Tatsuo et al. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems, v. 12, n. 2, p. 82-88, 2017Tradução . . Disponível em: https://doi.org/10.29292/jics.v12i2.455. Acesso em: 15 nov. 2025.
    • APA

      Itocazu, V. T., Sonnenberg, V., Martino, J. A., Simoen, E., & Claeys, C. (2017). Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems, 12( 2), 82-88. doi:10.29292/jics.v12i2.455
    • NLM

      Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies [Internet]. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v12i2.455
    • Vancouver

      Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies [Internet]. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v12i2.455
  • Fonte: Journal of Integrated Circuits and Systems. Unidade: EP

    Assunto: SEMICONDUTORES

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    • ABNT

      ITOCAZU, Vitor Tatsuo et al. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems, v. 12, n. 2, p. 101-106, 2016Tradução . . Disponível em: https://doi.org/10.29292/jics.v12i2.458. Acesso em: 15 nov. 2025.
    • APA

      Itocazu, V. T., Martino, J. A., Sasaki, K. R. A., Simoen, E., Claeys, C., & Sonnenberg, V. (2016). Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems, 12( 2), 101-106. doi:10.29292/jics.v12i2.458
    • NLM

      Itocazu VT, Martino JA, Sasaki KRA, Simoen E, Claeys C, Sonnenberg V. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation [Internet]. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v12i2.458
    • Vancouver

      Itocazu VT, Martino JA, Sasaki KRA, Simoen E, Claeys C, Sonnenberg V. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation [Internet]. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v12i2.458
  • Fonte: Journal of Integrated Circuits and Systems. Unidade: EP

    Assuntos: MICROELETRÔNICA, RAIOS X

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    • ABNT

      TEIXEIRA, Fernando Ferrari et al. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs. Journal of Integrated Circuits and Systems, v. 9, n. 2, p. 97-102, 2014Tradução . . Disponível em: https://doi.org/10.29292/jics.v9i2.394. Acesso em: 15 nov. 2025.
    • APA

      Teixeira, F. F., Martino, J. A., Bordallo, C. C. M., Silveira, M. A. G. da, Agopian, P. G. D., Simoen, E., & Claeys, C. (2014). Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs. Journal of Integrated Circuits and Systems, 9( 2), 97-102. doi:10.29292/jics.v9i2.394
    • NLM

      Teixeira FF, Martino JA, Bordallo CCM, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 97-102.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v9i2.394
    • Vancouver

      Teixeira FF, Martino JA, Bordallo CCM, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 97-102.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v9i2.394
  • Fonte: Journal of Integrated Circuits and Systems. Unidade: EP

    Assunto: MICROELETRÔNICA

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    • ABNT

      NISSIMOFF, Albert et al. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, v. 9, n. 2, p. 91-96, 2014Tradução . . Disponível em: https://doi.org/10.29292/jics.v9i2.393. Acesso em: 15 nov. 2025.
    • APA

      Nissimoff, A., Claeys, C., Aoulaiche, M., Sasaki, K. L. M., Simoen, E., & Martino, J. A. (2014). Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, 9( 2), 91-96. doi:10.29292/jics.v9i2.393
    • NLM

      Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v9i2.393
    • Vancouver

      Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v9i2.393
  • Fonte: Journal of Integrated Circuits and Systems. Unidade: EP

    Assunto: NANOELETRÔNICA

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    • ABNT

      MARTINO, Márcio Dalla Valle et al. Nanowire Tunnel Field Effect Transistors at High Temperature. Journal of Integrated Circuits and Systems, v. 8, n. 2, p. 110-115, 2013Tradução . . Disponível em: https://doi.org/10.29292/jics.v8i2.381. Acesso em: 15 nov. 2025.
    • APA

      Martino, M. D. V., Neves, F. S., Agopian, P. G. D., Martino, J. A., Rooyackers, R., & Claeys, C. (2013). Nanowire Tunnel Field Effect Transistors at High Temperature. Journal of Integrated Circuits and Systems, 8( 2), 110-115. doi:10.29292/jics.v8i2.381
    • NLM

      Martino MDV, Neves FS, Agopian PGD, Martino JA, Rooyackers R, Claeys C. Nanowire Tunnel Field Effect Transistors at High Temperature [Internet]. Journal of Integrated Circuits and Systems. 2013 ;8( 2): 110-115.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v8i2.381
    • Vancouver

      Martino MDV, Neves FS, Agopian PGD, Martino JA, Rooyackers R, Claeys C. Nanowire Tunnel Field Effect Transistors at High Temperature [Internet]. Journal of Integrated Circuits and Systems. 2013 ;8( 2): 110-115.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v8i2.381
  • Fonte: Journal of Integrated Circuits and Systems. Unidade: EP

    Assunto: TRANSISTORES

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    • ABNT

      SANTOS, Sara Dereste dos et al. Impact of selective epitaxial growth and uniaxial/biaxial strain on DIBL effect using triple gate FinFETs. Journal of Integrated Circuits and Systems, v. 5, n. 2, p. 154-159, 2010Tradução . . Disponível em: https://doi.org/10.29292/jics.v5i2.322. Acesso em: 15 nov. 2025.
    • APA

      Santos, S. D. dos, Martino, J. A., Simoen, E., & Claeys, C. (2010). Impact of selective epitaxial growth and uniaxial/biaxial strain on DIBL effect using triple gate FinFETs. Journal of Integrated Circuits and Systems, 5( 2), 154-159. doi:10.29292/jics.v5i2.322
    • NLM

      Santos SD dos, Martino JA, Simoen E, Claeys C. Impact of selective epitaxial growth and uniaxial/biaxial strain on DIBL effect using triple gate FinFETs [Internet]. Journal of Integrated Circuits and Systems. 2010 ;5( 2): 154-159.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v5i2.322
    • Vancouver

      Santos SD dos, Martino JA, Simoen E, Claeys C. Impact of selective epitaxial growth and uniaxial/biaxial strain on DIBL effect using triple gate FinFETs [Internet]. Journal of Integrated Circuits and Systems. 2010 ;5( 2): 154-159.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v5i2.322
  • Fonte: Journal of Integrated Circuits and Systems. Unidade: EP

    Assunto: TRANSISTORES

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    • ABNT

      PAVANELLO, Marcelo Antonio et al. Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs. Journal of Integrated Circuits and Systems, v. 5, n. 2, p. 168-173, 2010Tradução . . Disponível em: https://doi.org/10.29292/jics.v5i2.324. Acesso em: 15 nov. 2025.
    • APA

      Pavanello, M. A., Martino, J. A., Simoen, E., Claeys, C., Rooyackers, R., & Collaert, N. (2010). Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs. Journal of Integrated Circuits and Systems, 5( 2), 168-173. doi:10.29292/jics.v5i2.324
    • NLM

      Pavanello MA, Martino JA, Simoen E, Claeys C, Rooyackers R, Collaert N. Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs [Internet]. Journal of Integrated Circuits and Systems. 2010 ;5( 2): 168-173.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v5i2.324
    • Vancouver

      Pavanello MA, Martino JA, Simoen E, Claeys C, Rooyackers R, Collaert N. Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs [Internet]. Journal of Integrated Circuits and Systems. 2010 ;5( 2): 168-173.[citado 2025 nov. 15 ] Available from: https://doi.org/10.29292/jics.v5i2.324

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