Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs (2010)
- Authors:
- USP affiliated authors: MARTINO, JOAO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- DOI: 10.29292/jics.v5i2.324
- Assunto: TRANSISTORES
- Language: Inglês
- Imprenta:
- Publisher place: Porto Alegre
- Date published: 2010
- Source:
- Título: Journal of Integrated Circuits and Systems
- ISSN: 1807-1953
- Volume/Número/Paginação/Ano: v.5, n.2, p. 168-173, 2010
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
PAVANELLO, Marcelo Antonio et al. Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs. Journal of Integrated Circuits and Systems, v. 5, n. 2, p. 168-173, 2010Tradução . . Disponível em: https://doi.org/10.29292/jics.v5i2.324. Acesso em: 21 jan. 2026. -
APA
Pavanello, M. A., Martino, J. A., Simoen, E., Claeys, C., Rooyackers, R., & Collaert, N. (2010). Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs. Journal of Integrated Circuits and Systems, 5( 2), 168-173. doi:10.29292/jics.v5i2.324 -
NLM
Pavanello MA, Martino JA, Simoen E, Claeys C, Rooyackers R, Collaert N. Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs [Internet]. Journal of Integrated Circuits and Systems. 2010 ;5( 2): 168-173.[citado 2026 jan. 21 ] Available from: https://doi.org/10.29292/jics.v5i2.324 -
Vancouver
Pavanello MA, Martino JA, Simoen E, Claeys C, Rooyackers R, Collaert N. Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs [Internet]. Journal of Integrated Circuits and Systems. 2010 ;5( 2): 168-173.[citado 2026 jan. 21 ] Available from: https://doi.org/10.29292/jics.v5i2.324 - A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs
- Sidewall angle influence on the finFET analog parameters
- Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures
- Low temperature operation of undoped body triple-gate finFETs from an analog perspective
- Behavior of graded-channel fully depleted SOI NMOSFET at high temperatures
Informações sobre o DOI: 10.29292/jics.v5i2.324 (Fonte: oaDOI API)
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