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Artigo de periodico
An enzymatic glucose biosensor using the BESOI MOSFET (2024)
Yojo, Leonardo Shimizu; Rangel, R C; Duarte, Pedro Henrique; Sasaki, Kátia Regina Akemi ; Martino, João Antonio
Source: Solid State Electronics. Unidade: EP
Subjects: GLICOSE, DRENAGEM, TRANSISTORES
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ABNT
YOJO, Leonardo Shimizu et al. An enzymatic glucose biosensor using the BESOI MOSFET. Solid State Electronics, v. 211, n. Ja 2024, p. 1-6, 2024Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108830. Acesso em: 16 out. 2024.
APA
Yojo, L. S., Rangel, R. C., Duarte, P. H., Sasaki, K. R. A., & Martino, J. A. (2024). An enzymatic glucose biosensor using the BESOI MOSFET. Solid State Electronics, 211( Ja 2024), 1-6. doi:10.1016/j.sse.2023.108830
NLM
Yojo LS, Rangel RC, Duarte PH, Sasaki KRA, Martino JA. An enzymatic glucose biosensor using the BESOI MOSFET [Internet]. Solid State Electronics. 2024 ;211( Ja 2024): 1-6.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108830
Vancouver
Yojo LS, Rangel RC, Duarte PH, Sasaki KRA, Martino JA. An enzymatic glucose biosensor using the BESOI MOSFET [Internet]. Solid State Electronics. 2024 ;211( Ja 2024): 1-6.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108830
Artigo de periodico
Study of ISFET for KCl sensing (2024)
Duarte, Pedro Henrique; Rangel, Ricardo Cardoso; Sasaki, Kátia Regina Akemi ; Martino, João Antonio
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, PERÓXIDO DE HIDROGÊNIO, SENSORES BIOMÉDICOS
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ABNT
DUARTE, Pedro Henrique et al. Study of ISFET for KCl sensing. Solid State Electronics, v. 219, p. 1-5, 2024Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2024.108974. Acesso em: 16 out. 2024.
APA
Duarte, P. H., Rangel, R. C., Sasaki, K. R. A., & Martino, J. A. (2024). Study of ISFET for KCl sensing. Solid State Electronics, 219, 1-5. doi:10.1016/j.sse.2024.108974
NLM
Duarte PH, Rangel RC, Sasaki KRA, Martino JA. Study of ISFET for KCl sensing [Internet]. Solid State Electronics. 2024 ; 219 1-5.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2024.108974
Vancouver
Duarte PH, Rangel RC, Sasaki KRA, Martino JA. Study of ISFET for KCl sensing [Internet]. Solid State Electronics. 2024 ; 219 1-5.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2024.108974
Artigo de periodico
Experimental study of MISHEMT from 450 K down to 200 K for analog applications (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS ANALÓGICOS, SEMICONDUTORES
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ABNT
PERINA, Welder Fernandes et al. Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, v. 208, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108742. Acesso em: 16 out. 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, 208, 1-4. doi:10.1016/j.sse.2023.108742
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Artigo de periodico
Cu-modified electrolyte-gated transistors based on reduced graphene oxide (2023)
Ferreira, Rafael Cintra Hensel ; Comisso, Nicola ; Musiani, Marco ; Sedona, Francesco ; Sambi, Mauro ; Cester, Andrea ; Lago, Nicolò ; Casalini, Stefano
Source: Journal of Materials Chemistry C. Unidade: IFSC
Subjects: COBRE, TRANSISTORES, ELETRÔNICA
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ABNT
FERREIRA, Rafael Cintra Hensel et al. Cu-modified electrolyte-gated transistors based on reduced graphene oxide. Journal of Materials Chemistry C, v. 11, n. 26, p. 8876-8884 + supplementary information, 2023Tradução . . Disponível em: https://doi.org/10.1039/d3tc00596h. Acesso em: 16 out. 2024.
APA
Ferreira, R. C. H., Comisso, N., Musiani, M., Sedona, F., Sambi, M., Cester, A., et al. (2023). Cu-modified electrolyte-gated transistors based on reduced graphene oxide. Journal of Materials Chemistry C, 11( 26), 8876-8884 + supplementary information. doi:10.1039/d3tc00596h
NLM
Ferreira RCH, Comisso N, Musiani M, Sedona F, Sambi M, Cester A, Lago N, Casalini S. Cu-modified electrolyte-gated transistors based on reduced graphene oxide [Internet]. Journal of Materials Chemistry C. 2023 ; 11( 26): 8876-8884 + supplementary information.[citado 2024 out. 16 ] Available from: https://doi.org/10.1039/d3tc00596h
Vancouver
Ferreira RCH, Comisso N, Musiani M, Sedona F, Sambi M, Cester A, Lago N, Casalini S. Cu-modified electrolyte-gated transistors based on reduced graphene oxide [Internet]. Journal of Materials Chemistry C. 2023 ; 11( 26): 8876-8884 + supplementary information.[citado 2024 out. 16 ] Available from: https://doi.org/10.1039/d3tc00596h
Artigo de periodico
Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies (2023)
Toledo, Rodrigo do Nascimento; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: CIRCUITOS ANALÓGICOS, TRANSISTORES
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ABNT
TOLEDO, Rodrigo do Nascimento e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies. Semiconductor Science and Technology, v. 38, n. 9, p. 1-12, 2023Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/aceb84. Acesso em: 16 out. 2024.
APA
Toledo, R. do N., Martino, J. A., & Agopian, P. G. D. (2023). Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies. Semiconductor Science and Technology, 38( 9), 1-12. doi:10.1088/1361-6641/aceb84
NLM
Toledo R do N, Martino JA, Agopian PGD. Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies [Internet]. Semiconductor Science and Technology. 2023 ; 38( 9): 1-12.[citado 2024 out. 16 ] Available from: https://doi.org/10.1088/1361-6641/aceb84
Vancouver
Toledo R do N, Martino JA, Agopian PGD. Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies [Internet]. Semiconductor Science and Technology. 2023 ; 38( 9): 1-12.[citado 2024 out. 16 ] Available from: https://doi.org/10.1088/1361-6641/aceb84
Artigo de periodico
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis (2023)
Silva, Wenita de Lima; Toledo, Rodrigo do Nascimento; Gonçalez Filho, Walter; Nogueira, Alexandro de Moraes; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS ANALÓGICOS, NANOTECNOLOGIA
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ABNT
SILVA, Wenita de Lima et al. Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis. Solid State Electronics, v. 202, p. 1-8, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108611. Acesso em: 16 out. 2024.
APA
Silva, W. de L., Toledo, R. do N., Gonçalez Filho, W., Nogueira, A. de M., Agopian, P. G. D., & Martino, J. A. (2023). Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis. Solid State Electronics, 202, 1-8. doi:10.1016/j.sse.2023.108611
NLM
Silva W de L, Toledo R do N, Gonçalez Filho W, Nogueira A de M, Agopian PGD, Martino JA. Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis [Internet]. Solid State Electronics. 2023 ; 202 1-8.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108611
Vancouver
Silva W de L, Toledo R do N, Gonçalez Filho W, Nogueira A de M, Agopian PGD, Martino JA. Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis [Internet]. Solid State Electronics. 2023 ; 202 1-8.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108611
Artigo de periodico
Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications (2023)
Silva, V C P; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, TEMPERATURA, NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS
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ABNT
SILVA, V C P et al. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, v. 208, p. 1-5, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108729. Acesso em: 16 out. 2024.
APA
Silva, V. C. P., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2023). Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, 208, 1-5. doi:10.1016/j.sse.2023.108729
NLM
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Vancouver
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Artigo de periodico
Experimental study of MISHEMT from 450k down to 200 k for analog applications (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS ANALÓGICOS, TEMPERATURA
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ABNT
PERINA, Welder Fernandes et al. Experimental study of MISHEMT from 450k down to 200 k for analog applications. Solid State Electronics, v. 208, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108742. Acesso em: 16 out. 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Experimental study of MISHEMT from 450k down to 200 k for analog applications. Solid State Electronics, 208, 1-4. doi:10.1016/j.sse.2023.108742
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450k down to 200 k for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450k down to 200 k for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Artigo de periodico
MISHEMT intrinsic voltage gain under multiple channel output characteristics (2023)
Canales, Bruno Godoy; Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
CANALES, Bruno Godoy et al. MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, v. 38, n. 11, p. 1-6, 2023Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/acfa1f. Acesso em: 16 out. 2024.
APA
Canales, B. G., Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, 38( 11), 1-6. doi:10.1088/1361-6641/acfa1f
NLM
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 out. 16 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Vancouver
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 out. 16 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Artigo de periodico
Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data (2022)
Toledo, Rodrigo do Nascimento; Silva, Wenita de Lima; Gonçalez Filho, Walter; Nogueira, Alexandro de Moraes; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, CONDUTIVIDADE ELÉTRICA
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ABNT
TOLEDO, Rodrigo do Nascimento et al. Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data. Solid State Electronics, v. 194, p. 1-4, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108328. Acesso em: 16 out. 2024.
APA
Toledo, R. do N., Silva, W. de L., Gonçalez Filho, W., Nogueira, A. de M., Martino, J. A., & Agopian, P. G. D. (2022). Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data. Solid State Electronics, 194, 1-4. doi:10.1016/j.sse.2022.108328
NLM
Toledo R do N, Silva W de L, Gonçalez Filho W, Nogueira A de M, Martino JA, Agopian PGD. Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data [Internet]. Solid State Electronics. 2022 ; 194 1-4.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2022.108328
Vancouver
Toledo R do N, Silva W de L, Gonçalez Filho W, Nogueira A de M, Martino JA, Agopian PGD. Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data [Internet]. Solid State Electronics. 2022 ; 194 1-4.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2022.108328
Artigo de periodico
Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C (2022)
Sousa, Julia Cristina Soares; Perina, Welder F; Rangel, Roberto; Simoen, Eddy ; Veloso, Anabela; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, TRANSISTORES
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ABNT
SOUSA, Julia Cristina Soares et al. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C. Solid State Electronics, v. 189, p. 1-9, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108238. Acesso em: 16 out. 2024.
APA
Sousa, J. C. S., Perina, W. F., Rangel, R., Simoen, E., Veloso, A., Martino, J. A., & Agopian, P. G. D. (2022). Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C. Solid State Electronics, 189, 1-9. doi:10.1016/j.sse.2022.108238
NLM
Sousa JCS, Perina WF, Rangel R, Simoen E, Veloso A, Martino JA, Agopian PGD. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C [Internet]. Solid State Electronics. 2022 ;189 1-9.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2022.108238
Vancouver
Sousa JCS, Perina WF, Rangel R, Simoen E, Veloso A, Martino JA, Agopian PGD. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C [Internet]. Solid State Electronics. 2022 ;189 1-9.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2022.108238
Artigo de periodico
Unrevealing the interaction between O2 molecules and poly(3-hexylthiophene-2,5-diyl) (P3HT) (2022)
Fernandes, Marcelo; Wrasse, Ernesto Osvaldo; Koyama, Caio Junji Kawata; Günther, Florian Steffen ; Coutinho, Douglas José
Source: RSC Advances. Unidade: IFSC
Subjects: MATERIAIS ELETRÔNICOS, DIODOS, TRANSISTORES, POLÍMEROS (MATERIAIS)
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ABNT
FERNANDES, Marcelo et al. Unrevealing the interaction between O2 molecules and poly(3-hexylthiophene-2,5-diyl) (P3HT). RSC Advances, v. 2022, n. 29, p. 18578-18584, 2022Tradução . . Disponível em: https://doi.org/10.1039/d2ra02969c. Acesso em: 16 out. 2024.
APA
Fernandes, M., Wrasse, E. O., Koyama, C. J. K., Günther, F. S., & Coutinho, D. J. (2022). Unrevealing the interaction between O2 molecules and poly(3-hexylthiophene-2,5-diyl) (P3HT). RSC Advances, 2022( 29), 18578-18584. doi:10.1039/d2ra02969c
NLM
Fernandes M, Wrasse EO, Koyama CJK, Günther FS, Coutinho DJ. Unrevealing the interaction between O2 molecules and poly(3-hexylthiophene-2,5-diyl) (P3HT) [Internet]. RSC Advances. 2022 ; 2022( 29): 18578-18584.[citado 2024 out. 16 ] Available from: https://doi.org/10.1039/d2ra02969c
Vancouver
Fernandes M, Wrasse EO, Koyama CJK, Günther FS, Coutinho DJ. Unrevealing the interaction between O2 molecules and poly(3-hexylthiophene-2,5-diyl) (P3HT) [Internet]. RSC Advances. 2022 ; 2022( 29): 18578-18584.[citado 2024 out. 16 ] Available from: https://doi.org/10.1039/d2ra02969c
Artigo de periodico
Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature (2022)
Silva, Vanessa Cristina Pereira da; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, ALTA TEMPERATURA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Vanessa Cristina Pereira da et al. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature. Solid State Electronics, v. 191, p. 1-8, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108267. Acesso em: 16 out. 2024.
APA
Silva, V. C. P. da, Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2022). Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature. Solid State Electronics, 191, 1-8. doi:10.1016/j.sse.2022.108267
NLM
Silva VCP da, Martino JA, Simoen E, Veloso A, Agopian PGD. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature [Internet]. Solid State Electronics. 2022 ;191 1-8.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2022.108267
Vancouver
Silva VCP da, Martino JA, Simoen E, Veloso A, Agopian PGD. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature [Internet]. Solid State Electronics. 2022 ;191 1-8.[citado 2024 out. 16 ] Available from: https://doi.org/10.1016/j.sse.2022.108267
Artigo de periodico
Characterizing BJTs using the Early voltage in the forward active mode (2018)
Costa, Luciano da Fontoura ; Silva, Filipi Nascimento; Comin, Cesar H.
Source: International Journal of Circuit Theory and Applications. Unidade: IFSC
Subjects: TRANSISTORES, CIRCUITOS ELETRÔNICOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
COSTA, Luciano da Fontoura e SILVA, Filipi Nascimento e COMIN, Cesar H. Characterizing BJTs using the Early voltage in the forward active mode. International Journal of Circuit Theory and Applications, v. 46, n. 4, p. 978-986, 2018Tradução . . Disponível em: https://doi.org/10.1002/cta.2450. Acesso em: 16 out. 2024.
APA
Costa, L. da F., Silva, F. N., & Comin, C. H. (2018). Characterizing BJTs using the Early voltage in the forward active mode. International Journal of Circuit Theory and Applications, 46( 4), 978-986. doi:10.1002/cta.2450
NLM
Costa L da F, Silva FN, Comin CH. Characterizing BJTs using the Early voltage in the forward active mode [Internet]. International Journal of Circuit Theory and Applications. 2018 ; 46( 4): 978-986.[citado 2024 out. 16 ] Available from: https://doi.org/10.1002/cta.2450
Vancouver
Costa L da F, Silva FN, Comin CH. Characterizing BJTs using the Early voltage in the forward active mode [Internet]. International Journal of Circuit Theory and Applications. 2018 ; 46( 4): 978-986.[citado 2024 out. 16 ] Available from: https://doi.org/10.1002/cta.2450
Artigo de periodico
Graphene field-effect transistor array with integrated electrolytic gates scaled to 200 mm (2016)
Vieira, N. C. S.; Borme, J.; Machado Junior, G.; Cerqueira, F.; Freitas, P. P.; Zucolotto, Valtencir ; Peres, N. M. R.; Alpuim, P.
Source: Journal of Physics: Condensed Matter. Unidade: IFSC
Subjects: TRANSISTORES, SENSORES QUÍMICOS, FOTOLITOGRAFIA
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ABNT
VIEIRA, N. C. S. et al. Graphene field-effect transistor array with integrated electrolytic gates scaled to 200 mm. Journal of Physics: Condensed Matter, v. 28, n. 8, p. 085302-1-085302-9, 2016Tradução . . Disponível em: https://doi.org/10.1088/0953-8984/28/8/085302. Acesso em: 16 out. 2024.
APA
Vieira, N. C. S., Borme, J., Machado Junior, G., Cerqueira, F., Freitas, P. P., Zucolotto, V., et al. (2016). Graphene field-effect transistor array with integrated electrolytic gates scaled to 200 mm. Journal of Physics: Condensed Matter, 28( 8), 085302-1-085302-9. doi:10.1088/0953-8984/28/8/085302
NLM
Vieira NCS, Borme J, Machado Junior G, Cerqueira F, Freitas PP, Zucolotto V, Peres NMR, Alpuim P. Graphene field-effect transistor array with integrated electrolytic gates scaled to 200 mm [Internet]. Journal of Physics: Condensed Matter. 2016 ; 28( 8): 085302-1-085302-9.[citado 2024 out. 16 ] Available from: https://doi.org/10.1088/0953-8984/28/8/085302
Vancouver
Vieira NCS, Borme J, Machado Junior G, Cerqueira F, Freitas PP, Zucolotto V, Peres NMR, Alpuim P. Graphene field-effect transistor array with integrated electrolytic gates scaled to 200 mm [Internet]. Journal of Physics: Condensed Matter. 2016 ; 28( 8): 085302-1-085302-9.[citado 2024 out. 16 ] Available from: https://doi.org/10.1088/0953-8984/28/8/085302
Artigo de periodico
Modeling of peak voltage and current of nanowire resonant tunneling devices: case study on InAs/InP double-barrier heterostructures (2013)
Pereira, Regiane Aparecida Ragi; Nobrega, Rafael Vinicius Tayette da; Romero, Murilo Araújo
Source: International Journal of Numerical Modelling. Unidade: EESC
Subjects: TRANSISTORES, NANOELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PEREIRA, Regiane Aparecida Ragi e NOBREGA, Rafael Vinicius Tayette da e ROMERO, Murilo Araújo. Modeling of peak voltage and current of nanowire resonant tunneling devices: case study on InAs/InP double-barrier heterostructures. International Journal of Numerical Modelling, v. 26, n. 5, p. 506-517, 2013Tradução . . Disponível em: https://doi.org/10.1002/jnm.1911. Acesso em: 16 out. 2024.
APA
Pereira, R. A. R., Nobrega, R. V. T. da, & Romero, M. A. (2013). Modeling of peak voltage and current of nanowire resonant tunneling devices: case study on InAs/InP double-barrier heterostructures. International Journal of Numerical Modelling, 26( 5), 506-517. doi:10.1002/jnm.1911
NLM
Pereira RAR, Nobrega RVT da, Romero MA. Modeling of peak voltage and current of nanowire resonant tunneling devices: case study on InAs/InP double-barrier heterostructures [Internet]. International Journal of Numerical Modelling. 2013 ; 26( 5): 506-517.[citado 2024 out. 16 ] Available from: https://doi.org/10.1002/jnm.1911
Vancouver
Pereira RAR, Nobrega RVT da, Romero MA. Modeling of peak voltage and current of nanowire resonant tunneling devices: case study on InAs/InP double-barrier heterostructures [Internet]. International Journal of Numerical Modelling. 2013 ; 26( 5): 506-517.[citado 2024 out. 16 ] Available from: https://doi.org/10.1002/jnm.1911
Artigo de periodico
A novel self consistent calculation approach for the capacitance-voltage characteristics of semiconductor quantum wire transistors based on a split-gate configuration (2012)
Ragi, Regiane; Nóbrega, Rafael Vinícius Tayette da; Romero, Murilo Araujo
Source: COMPEL : the international journal for computation and mathematics in electrical and electronic engineering. Unidade: EESC
Subjects: SEMICONDUTORES, TRANSISTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
RAGI, Regiane e NÓBREGA, Rafael Vinícius Tayette da e ROMERO, Murilo Araujo. A novel self consistent calculation approach for the capacitance-voltage characteristics of semiconductor quantum wire transistors based on a split-gate configuration. COMPEL : the international journal for computation and mathematics in electrical and electronic engineering, v. 31, n. 2, p. 460-476, 2012Tradução . . Disponível em: https://doi.org/10.1108/03321641211200536. Acesso em: 16 out. 2024.
APA
Ragi, R., Nóbrega, R. V. T. da, & Romero, M. A. (2012). A novel self consistent calculation approach for the capacitance-voltage characteristics of semiconductor quantum wire transistors based on a split-gate configuration. COMPEL : the international journal for computation and mathematics in electrical and electronic engineering, 31( 2), 460-476. doi:10.1108/03321641211200536
NLM
Ragi R, Nóbrega RVT da, Romero MA. A novel self consistent calculation approach for the capacitance-voltage characteristics of semiconductor quantum wire transistors based on a split-gate configuration [Internet]. COMPEL : the international journal for computation and mathematics in electrical and electronic engineering. 2012 ; 31( 2): 460-476.[citado 2024 out. 16 ] Available from: https://doi.org/10.1108/03321641211200536
Vancouver
Ragi R, Nóbrega RVT da, Romero MA. A novel self consistent calculation approach for the capacitance-voltage characteristics of semiconductor quantum wire transistors based on a split-gate configuration [Internet]. COMPEL : the international journal for computation and mathematics in electrical and electronic engineering. 2012 ; 31( 2): 460-476.[citado 2024 out. 16 ] Available from: https://doi.org/10.1108/03321641211200536

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