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Artigo de periodico
Implementation of a millimeter-wave butler matrix on metallic nanowires-filled membrane platform (2024)
Verona, Bruno Marinaro; Simionato, Eligia; Palomino, Gustavo; Aldaya, Ivan; Penchel, Rafael Abrantes; Serrano, Ariana Maria da Conceição Lacorte Caniato ; Rehder, Gustavo Pamplona
Source: IEEE Access. Unidade: EP
Subjects: WIRELESS, MICROELETRÔNICA, TELECOMUNICAÇÕES, MATRIZES
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VERONA, Bruno Marinaro et al. Implementation of a millimeter-wave butler matrix on metallic nanowires-filled membrane platform. IEEE Access, v. 12, n. Ja 2024, p. 22132-22143, 2024Tradução . . Disponível em: https://doi.org/10.1109/ACCESS.2024.3357078. Acesso em: 25 set. 2024.
APA
Verona, B. M., Simionato, E., Palomino, G., Aldaya, I., Penchel, R. A., Serrano, A. M. da C. L. C., & Rehder, G. P. (2024). Implementation of a millimeter-wave butler matrix on metallic nanowires-filled membrane platform. IEEE Access, 12( Ja 2024), 22132-22143. doi:10.1109/ACCESS.2024.3357078
NLM
Verona BM, Simionato E, Palomino G, Aldaya I, Penchel RA, Serrano AM da CLC, Rehder GP. Implementation of a millimeter-wave butler matrix on metallic nanowires-filled membrane platform [Internet]. IEEE Access. 2024 ; 12( Ja 2024): 22132-22143.[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/ACCESS.2024.3357078
Vancouver
Verona BM, Simionato E, Palomino G, Aldaya I, Penchel RA, Serrano AM da CLC, Rehder GP. Implementation of a millimeter-wave butler matrix on metallic nanowires-filled membrane platform [Internet]. IEEE Access. 2024 ; 12( Ja 2024): 22132-22143.[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/ACCESS.2024.3357078
Trabalho de evento
Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs (2023)
Araújo, Gustavo Vinicius de; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS ANALÓGICOS, MICROELETRÔNICA, MATERIAIS NANOESTRUTURADOS
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ARAÚJO, Gustavo Vinicius de e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs. 2023, Anais.. [Piscataway, N.J.]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302603. Acesso em: 25 set. 2024.
APA
Araújo, G. V. de, Martino, J. A., & Agopian, P. G. D. (2023). Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs. In SBMicro. [Piscataway, N.J.]: IEEE. doi:10.1109/SBMicro60499.2023.10302603
NLM
Araújo GV de, Martino JA, Agopian PGD. Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs [Internet]. SBMicro. 2023 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302603
Vancouver
Araújo GV de, Martino JA, Agopian PGD. Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs [Internet]. SBMicro. 2023 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302603
Trabalho de evento
Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET (2023)
Ramos, Daniel Augusto; Sasaki, Kátia Regina Akemi ; Rangel, Ricardo Cardoso; Duarte, Pedro Henrique; Martino, João Antonio
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices. Unidade: EP
Subjects: DISPOSITIVOS ELETRÔNICOS, TRANSISTORES, MICROELETRÔNICA
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RAMOS, Daniel Augusto et al. Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET. 2023, Anais.. [Piscataway, N.J.]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302644. Acesso em: 25 set. 2024.
APA
Ramos, D. A., Sasaki, K. R. A., Rangel, R. C., Duarte, P. H., & Martino, J. A. (2023). Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET. In SBMicro. [Piscataway, N.J.]: IEEE. doi:10.1109/SBMicro60499.2023.10302644
NLM
Ramos DA, Sasaki KRA, Rangel RC, Duarte PH, Martino JA. Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET [Internet]. SBMicro. 2023 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302644
Vancouver
Ramos DA, Sasaki KRA, Rangel RC, Duarte PH, Martino JA. Influence of the source/drain doping region on the reconfigurability of BESOI MOSFET [Internet]. SBMicro. 2023 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302644
Trabalho de evento
Trade-off between channel length and mechanical stress in the operational transconductance amplifier designed with SOI FinFET (2023)
Ribeiro, Arllen D.R; Araújo, Gustavo Vinicius de; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices. Unidade: EP
Subjects: DISPOSITIVOS ELETRÔNICOS, TRANSISTORES, MICROELETRÔNICA
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RIBEIRO, Arllen D.R et al. Trade-off between channel length and mechanical stress in the operational transconductance amplifier designed with SOI FinFET. 2023, Anais.. [Piscataway, N.J.]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302575. Acesso em: 25 set. 2024.
APA
Ribeiro, A. D. R., Araújo, G. V. de, Martino, J. A., & Agopian, P. G. D. (2023). Trade-off between channel length and mechanical stress in the operational transconductance amplifier designed with SOI FinFET. In SBMicro. [Piscataway, N.J.]: IEEE. doi:10.1109/SBMicro60499.2023.10302575
NLM
Ribeiro ADR, Araújo GV de, Martino JA, Agopian PGD. Trade-off between channel length and mechanical stress in the operational transconductance amplifier designed with SOI FinFET [Internet]. SBMicro. 2023 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302575
Vancouver
Ribeiro ADR, Araújo GV de, Martino JA, Agopian PGD. Trade-off between channel length and mechanical stress in the operational transconductance amplifier designed with SOI FinFET [Internet]. SBMicro. 2023 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302575
Trabalho de evento
Analysis of low-dropout voltage regulator designed with gate-all-around nanosheet transistors (2023)
Souto, Rayana Carvalho de Barros; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices. Unidade: EP
Subjects: TRANSISTORES, MICROELETRÔNICA, MATERIAIS NANOESTRUTURADOS
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SOUTO, Rayana Carvalho de Barros e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Analysis of low-dropout voltage regulator designed with gate-all-around nanosheet transistors. 2023, Anais.. [Piscataway]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302596. Acesso em: 25 set. 2024.
APA
Souto, R. C. de B., Martino, J. A., & Agopian, P. G. D. (2023). Analysis of low-dropout voltage regulator designed with gate-all-around nanosheet transistors. In SBMicro. [Piscataway]: IEEE. doi:10.1109/SBMicro60499.2023.10302596
NLM
Souto RC de B, Martino JA, Agopian PGD. Analysis of low-dropout voltage regulator designed with gate-all-around nanosheet transistors [Internet]. SBMicro. 2023 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302596
Vancouver
Souto RC de B, Martino JA, Agopian PGD. Analysis of low-dropout voltage regulator designed with gate-all-around nanosheet transistors [Internet]. SBMicro. 2023 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302596
Artigo de periodico
Ultrasensitive diamond microelectrode application in the detection of Ca2+ transport by annexinA5-containing nanostructured liposomes (2022)
Pasquarelli, Alberto; Andrilli, Luiz Henrique da Silva ; Bolean, Maytê ; Ferreira, Claudio Reis; Cruz, Marcos Antônio Eufrasio ; Oliveira, Flávia Amadeu de; Ramos, Ana Paula ; Millán, José Luis; Bottini, Massimo; Ciancaglini, Pietro
Source: Biosensors. Unidade: FFCLRP
Subjects: MICROELETRÔNICA, ELETRODO, DIAMANTE, TRANSPORTE DE CÁLCIO
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PASQUARELLI, Alberto et al. Ultrasensitive diamond microelectrode application in the detection of Ca2+ transport by annexinA5-containing nanostructured liposomes. Biosensors, v. 12, n. 7, p. 1-15, 2022Tradução . . Disponível em: https://doi.org/10.3390/bios12070525. Acesso em: 25 set. 2024.
APA
Pasquarelli, A., Andrilli, L. H. da S., Bolean, M., Ferreira, C. R., Cruz, M. A. E., Oliveira, F. A. de, et al. (2022). Ultrasensitive diamond microelectrode application in the detection of Ca2+ transport by annexinA5-containing nanostructured liposomes. Biosensors, 12( 7), 1-15. doi:10.3390/bios12070525
NLM
Pasquarelli A, Andrilli LH da S, Bolean M, Ferreira CR, Cruz MAE, Oliveira FA de, Ramos AP, Millán JL, Bottini M, Ciancaglini P. Ultrasensitive diamond microelectrode application in the detection of Ca2+ transport by annexinA5-containing nanostructured liposomes [Internet]. Biosensors. 2022 ; 12( 7): 1-15.[citado 2024 set. 25 ] Available from: https://doi.org/10.3390/bios12070525
Vancouver
Pasquarelli A, Andrilli LH da S, Bolean M, Ferreira CR, Cruz MAE, Oliveira FA de, Ramos AP, Millán JL, Bottini M, Ciancaglini P. Ultrasensitive diamond microelectrode application in the detection of Ca2+ transport by annexinA5-containing nanostructured liposomes [Internet]. Biosensors. 2022 ; 12( 7): 1-15.[citado 2024 set. 25 ] Available from: https://doi.org/10.3390/bios12070525
Trabalho de evento
Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's (2022)
Ribeiro, Arllen D.R.; Araújo, Gustavo Vinicius de; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: SBMICRO. Conference titles: Symposium on Microelectronics Technology. Unidade: EP
Subjects: MICROELETRÔNICA, SILÍCIO, INOVAÇÕES TECNOLÓGICAS
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RIBEIRO, Arllen D.R. et al. Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's. 2022, Anais.. Piscataway: IEEE, 2022. Disponível em: https://doi.org/10.1109/SBMICRO55822.2022.9881005. Acesso em: 25 set. 2024.
APA
Ribeiro, A. D. R., Araújo, G. V. de, Martino, J. A., & Agopian, P. G. D. (2022). Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's. In SBMICRO. Piscataway: IEEE. doi:10.1109/SBMICRO55822.2022.9881005
NLM
Ribeiro ADR, Araújo GV de, Martino JA, Agopian PGD. Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's [Internet]. SBMICRO. 2022 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9881005
Vancouver
Ribeiro ADR, Araújo GV de, Martino JA, Agopian PGD. Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's [Internet]. SBMICRO. 2022 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9881005
Dissertação (Mestrado)
Estudo de transistores de nanofolha de silício com porta ao redor em baixas temperaturas (2022)
Leal, João Vitor da Costa; Martino, João Antonio (Orientador) ; Der Agopian, Paula Ghedini (coorient)
Unidade: EP
Subjects: TRANSISTORES, MICROELETRÔNICA, BAIXA TEMPERATURA
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LEAL, João Vitor da Costa. Estudo de transistores de nanofolha de silício com porta ao redor em baixas temperaturas. 2022. Dissertação (Mestrado) – Universidade de São Paulo, São Paulo, 2022. Disponível em: https://www.teses.usp.br/teses/disponiveis/3/3140/tde-20042022-082639/. Acesso em: 25 set. 2024.
APA
Leal, J. V. da C. (2022). Estudo de transistores de nanofolha de silício com porta ao redor em baixas temperaturas (Dissertação (Mestrado). Universidade de São Paulo, São Paulo. Recuperado de https://www.teses.usp.br/teses/disponiveis/3/3140/tde-20042022-082639/
NLM
Leal JV da C. Estudo de transistores de nanofolha de silício com porta ao redor em baixas temperaturas [Internet]. 2022 ;[citado 2024 set. 25 ] Available from: https://www.teses.usp.br/teses/disponiveis/3/3140/tde-20042022-082639/
Vancouver
Leal JV da C. Estudo de transistores de nanofolha de silício com porta ao redor em baixas temperaturas [Internet]. 2022 ;[citado 2024 set. 25 ] Available from: https://www.teses.usp.br/teses/disponiveis/3/3140/tde-20042022-082639/
Tese (Doutorado)
Estudo dos transistores de tunelamento por efeito de campo como biossensores (2021)
Macambira, Christian Nemeth; Martino, João Antonio (Orientador) ; Agopian, Paula Ghedini Der (coorient)
Unidade: EP
Subjects: MICROELETRÔNICA, TRANSISTORES
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ABNT
MACAMBIRA, Christian Nemeth. Estudo dos transistores de tunelamento por efeito de campo como biossensores. 2021. Tese (Doutorado) – Universidade de São Paulo, São Paulo, 2021. Disponível em: https://www.teses.usp.br/teses/disponiveis/3/3140/tde-04032022-085035/. Acesso em: 25 set. 2024.
APA
Macambira, C. N. (2021). Estudo dos transistores de tunelamento por efeito de campo como biossensores (Tese (Doutorado). Universidade de São Paulo, São Paulo. Recuperado de https://www.teses.usp.br/teses/disponiveis/3/3140/tde-04032022-085035/
NLM
Macambira CN. Estudo dos transistores de tunelamento por efeito de campo como biossensores [Internet]. 2021 ;[citado 2024 set. 25 ] Available from: https://www.teses.usp.br/teses/disponiveis/3/3140/tde-04032022-085035/
Vancouver
Macambira CN. Estudo dos transistores de tunelamento por efeito de campo como biossensores [Internet]. 2021 ;[citado 2024 set. 25 ] Available from: https://www.teses.usp.br/teses/disponiveis/3/3140/tde-04032022-085035/
Trabalho de evento
Liquid helium temperature operation of graded-channel SOI nMOSFETs (2012)
Souza, Michelly de ; Kilchytska, Valeriya ; Flandre, Denis ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SOUZA, Michelly de et al. Liquid helium temperature operation of graded-channel SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0135ecst. Acesso em: 25 set. 2024.
APA
Souza, M. de, Kilchytska, V., Flandre, D., & Pavanello, M. A. (2012). Liquid helium temperature operation of graded-channel SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0135ecst
NLM
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0135ecst
Vancouver
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0135ecst
Trabalho de evento
Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements (2012)
Mariniello, Genaro ; Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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MARINIELLO, Genaro et al. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0231ecst. Acesso em: 25 set. 2024.
APA
Mariniello, G., Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0231ecst
NLM
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0231ecst
Vancouver
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0231ecst
Trabalho de evento
Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI (2012)
Caño de Andrade, Maria Glória ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
CAÑO DE ANDRADE, Maria Glória et al. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0111ecst. Acesso em: 25 set. 2024.
APA
Caño de Andrade, M. G., Martino, J. A., Simoen, E., & Claeys, C. (2012). Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0111ecst
NLM
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0111ecst
Vancouver
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0111ecst
Trabalho de evento
Temperature influence on nanowire tunnel field effect transistors (2012)
Neves, Felipe Souza; Martino, Márcio Dalla Valle; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Rooyackers, Rita ; Leonelli, Daniele ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
NEVES, Felipe Souza et al. Temperature influence on nanowire tunnel field effect transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0223ecst. Acesso em: 25 set. 2024.
APA
Neves, F. S., Martino, M. D. V., Agopian, P. G. D., Martino, J. A., Rooyackers, R., Leonelli, D., & Claeys, C. (2012). Temperature influence on nanowire tunnel field effect transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0223ecst
NLM
Neves FS, Martino MDV, Agopian PGD, Martino JA, Rooyackers R, Leonelli D, Claeys C. Temperature influence on nanowire tunnel field effect transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0223ecst
Vancouver
Neves FS, Martino MDV, Agopian PGD, Martino JA, Rooyackers R, Leonelli D, Claeys C. Temperature influence on nanowire tunnel field effect transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0223ecst
Trabalho de evento
On the variability of the low-frequency noise in UTBOX SOI nMOSFETs (2012)
Simoen, Eddy ; Caño de Andrade, Maria Glória ; Almeida, Luciano Mendes; Aoulaiche, Marc; Caillat, Christian; Jurczak, Malgorzata; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SIMOEN, Eddy et al. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0051ecst. Acesso em: 25 set. 2024.
APA
Simoen, E., Caño de Andrade, M. G., Almeida, L. M., Aoulaiche, M., Caillat, C., Jurczak, M., & Claeys, C. (2012). On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0051ecst
NLM
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0051ecst
Vancouver
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0051ecst
Trabalho de evento
Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors (2012)
Trevisoli, Renan ; Doria, Rodrigo Trevisoli ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
TREVISOLI, Renan et al. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0207ecst. Acesso em: 25 set. 2024.
APA
Trevisoli, R., Doria, R. T., Souza, M. de, & Pavanello, M. A. (2012). Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0207ecst
NLM
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0207ecst
Vancouver
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0207ecst
Trabalho de evento
Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response (2012)
Roque Huanca, Danilo ; Elias, Vinícius F; Salcedo, Walter Jaimes
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROQUE HUANCA, Danilo e ELIAS, Vinícius F e SALCEDO, Walter Jaimes. Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0315ecst. Acesso em: 25 set. 2024.
APA
Roque Huanca, D., Elias, V. F., & Salcedo, W. J. (2012). Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0315ecst
NLM
Roque Huanca D, Elias VF, Salcedo WJ. Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0315ecst
Vancouver
Roque Huanca D, Elias VF, Salcedo WJ. Porous silicon photonic crystals: influence of electrolyte composition on the nanostructure and the optical response [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0315ecst
Trabalho de evento
Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS (2012)
Santos, Sara Dereste dos ; Nicoletti, Talitha; Aoulaiche, Marc; Martino, João Antonio ; Veloso, A; Jurczak, Malgorzata; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SANTOS, Sara Dereste dos et al. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf. Acesso em: 25 set. 2024.
APA
Santos, S. D. dos, Nicoletti, T., Aoulaiche, M., Martino, J. A., Veloso, A., Jurczak, M., et al. (2012). Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. Recuperado de https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
NLM
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Vancouver
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Trabalho de evento
Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance (2012)
Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
DORIA, Rodrigo Trevisoli et al. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0215ecst. Acesso em: 25 set. 2024.
APA
Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0215ecst
NLM
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0215ecst
Vancouver
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0215ecst
Trabalho de evento
Simulation of PECVD SiO2 deposition using a cellular automata approach (2012)
Colombo, Fábio Belotti; Páez Carreño, Marcelo Nelson
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
COLOMBO, Fábio Belotti e PÁEZ CARREÑO, Marcelo Nelson. Simulation of PECVD SiO2 deposition using a cellular automata approach. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0297ecst. Acesso em: 25 set. 2024.
APA
Colombo, F. B., & Páez Carreño, M. N. (2012). Simulation of PECVD SiO2 deposition using a cellular automata approach. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0297ecst
NLM
Colombo FB, Páez Carreño MN. Simulation of PECVD SiO2 deposition using a cellular automata approach [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0297ecst
Vancouver
Colombo FB, Páez Carreño MN. Simulation of PECVD SiO2 deposition using a cellular automata approach [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0297ecst
Trabalho de evento
TiO2 nanotubes production and characterization (2012)
Fraga, Tiago Marques; Albertin, Katia Franklin ; Pereyra, Inés
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
FRAGA, Tiago Marques e ALBERTIN, Katia Franklin e PEREYRA, Inés. TiO2 nanotubes production and characterization. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0199ecst. Acesso em: 25 set. 2024.
APA
Fraga, T. M., Albertin, K. F., & Pereyra, I. (2012). TiO2 nanotubes production and characterization. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0199ecst
NLM
Fraga TM, Albertin KF, Pereyra I. TiO2 nanotubes production and characterization [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0199ecst
Vancouver
Fraga TM, Albertin KF, Pereyra I. TiO2 nanotubes production and characterization [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0199ecst

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